Xilinx V2.1 - Manuals

5 Contents Chapter 1 Introduction Industry and Product Overview ................................................................................. 8 System Generator ..................................................................................................... 9 System Level Modeling with Syst...

8 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Chapter 1 Introduction This chapter describes the basic concepts and tools of the System Generator v2.1. This chapter contains the following sections. • Industry and Product Overview • System Generator • System Level Modeling w...

System Generator 9 Introduction constructs for simulation, its synthesizable subset is far too restrictive for systemdesign. System Generator is a software tool for modeling and designing FPGA-based DSPsystems in Simulink. The tool presents a high level abstract view of a DSP system, yetnevertheless...

10 Xilinx Development System Xilinx System Generator v2.1 Reference Guide 3 and simply use floating point operations in hardware. The answer is that mostoperations have a sufficiently small dynamic range that a fixed point representation isacceptable, and the hardware realization of fixed point is c...

The System Generator Design Flow 11 Introduction The System Generator design flow is shown in the following figure. Figure 1-1: System Generator design flow diagram The Xilinx Blockset is accessible in the Simulink library browser, and elements can befreely combined with other Simulink elements. Onl...

12 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Simulink hierarchy into a hierarchical VHDL netlist. In addition, System Generatorcreates the necessary command files to create the IP block netlists using COREGenerator  , invokes CORE Generator, and creates project and scri...

Hardware Handshaking 13 Introduction Generator then propagates signal types and precisions as appropriate. Theautomatically chosen type is the least expensive that preserves full precision.Translations from signed to unsigned and vice versa are automatic as well. System Generator also allows designs...

14 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Bit-True and Cycle-True Modeling System Generator produces a hardware implementation that is bit and cycle true tothe system level simulation. We define the term bit and cycle true at the boundaries ofthe design. The boundarie...

What is a Xilinx Block? 15 Xilinx Blockset Overview Chapter 2 Xilinx Blockset Overview This chapter gives an overview of the Xilinx Blockset, including backgroundinformation on underlying blockset implementation, which will help you understandhow each block can be used to create and simulate your de...

16 Xilinx Development System Xilinx System Generator v2.1 Reference Guide portion of a Simulink model to be implemented in an FPGA must be built exclusivelyof Xilinx blocks, with the exception of subsystems denoted as black boxes. Instantiating Xilinx Blocks within a Simulink Model Xilinx blocks can...

The Nature of Signals in the Xilinx Blockset 17 Xilinx Blockset Overview As an example, the figures shown below depict the Xilinx Negate block parametersdialog box with full and user defined precision. Note in the latter case the additionaloptions for selecting quantization and overflow behavior. Fi...

18 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Use of Xilinx Smart-IP Cores by the System Generator To increase hardware performance, most System Generator blocks are implementedusing Xilinx Smart-IP (Intellectual Property) LogiCOREs. These are hand craftedmodules that mak...

Common Options in Block Parameters Dialog Box 19 Xilinx Blockset Overview Xilinx LogiCORE  Versions The Xilinx LogiCORE  blocks (indicating the version numbers being supported by the System Generator) used in Xilinx System Generator v2.1 are listed below. Common Options in Block Parameters Dialog ...

20 Xilinx Development System Xilinx System Generator v2.1 Reference Guide specific parameters are described in the specific block documentation in the nextchapter. The remainder of the parameters in each block’s parameters dialog box are commonto most blocks. These common parameters are described be...

Common Options in Block Parameters Dialog Box 21 Xilinx Blockset Overview Precision The fundamental computational mode in the Xilinx Blockset is arbitrary precisionfixed point arithmetic. Most blocks give you the option of choosing the precision, i.e.the number of bits and binary point position. By ...

22 Xilinx Development System Xilinx System Generator v2.1 Reference Guide In the Simulink environment, the Override with Doubles option allows you tosimulate the entire design in double precision floating point. This option is useful in selecting fixed point widths or when debugging. If you detectun...

Basic Elements 23 Xilinx Blocks Chapter 3 Xilinx Blocks This chapter describes each Xilinx block in detail. Xilinx blocks are grouped within sixcategories, also shown in the Simulink library browser. They are: • Basic Elements • Communication • DSP • Math • MATLAB I/O • Memory • State Machine Basic ...

24 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-1: System Generator block parameters dialog box Parameters specific to the System Generator...

26 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Addressable Shift Register The Xilinx Addressable Shift Register block is a variable-lengthshift register (or delay chain). This block differs from the XilinxDelay block in that the amount of latency experienced by datafrom in...

28 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Black Box The Xilinx Black Box token enables you to instantiate your ownspecialized functions in your model, and subsequently into a generateddesign. Like the System Generator token, the Black Box token can beplaced in any Sim...

Basic Elements 29 Xilinx Blocks infer them in the generated VHDL. The block parameters dialog box can be invokedby double-clicking the icon in your Simulink model. Figure 3-3: Black Box block parameters dialog box Parameters specified as cell arrays (generic or parameter names, types, and values)per...

30 Xilinx Development System Xilinx System Generator v2.1 Reference Guide input and output ports respectively. To configure the black box, enter the parametersin the black box block parameters dialog box as shown in the figure below. Figure 3-4: Customizing Clocks in the Black Box block parameters d...

Basic Elements 31 Xilinx Blocks Constant The Xilinx Constant block generates a constant. This block is similar to theSimulink constant block, but can be used to drive the inputs on Xilinxblocks. Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in...

32 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-7: Convert block parameters dialog box All the parameters of the Convert block are paramete...

34 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The Counter block parameters dialog box is invoked by double-clicking the blockicon. Figure 3-8: Counter block parameters dialog box Parameters specific to the block are: • Number of Bits : specifie...

Basic Elements 35 Xilinx Blocks Xilinx LogiCORE The block always uses the Xilinx LogiCORE: Binary Counter V5.0. The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\binary_counter.pdf Delay The Xilinx Delay block is a delay line (als...

36 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Down Sample The Xilinx Down Sample block reduces the sample rate at the pointwhere the block is placed in your design. The input signal is under-sampled so that every nth input sample is presented at the output andheld. Output...

Basic Elements 37 Xilinx Blocks Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-12: Down sample block parameters dialog box Parameters specific to the block are: • Sampling Rate : must be an integer greater or equ...

38 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Mux The Xilinx Mux block implements a multiplexer. The block has one select input (type unsigned) and a user-configurable number of data bus inputs, ranging from 2 to32. Block Parameters Dialog Box The block parameters dialog ...

Basic Elements 39 Xilinx Blocks %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\bus_mux.pdf Parallel to Serial The Parallel to Serial block takes an input word and splits it into N timemultiplexed output words where N equals the number of input bits/number of output bits. The order ...

40 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box Figure 3-15: Parallel to Serial block parameters dialog box Parameters specific to the block are: • Output Order : Most significant word first or least significant word first. Word size is determine...

Basic Elements 41 Xilinx Blocks Block Interface The block has one input port for the data and an optional input reset port. The initialoutput value is specified by the user in the block parameters dialog box (below). Datapresented at the input will appear at the output after one sample period. Upon ...

42 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Reinterpret The Reinterpret block forces its output to a new type without anyregard for retaining the numerical value represented by the input. Thebinary representation is passed through unchanged, so in hardware thisblock con...

Basic Elements 43 Xilinx Blocks Block Parameters Dialog box Figure 3-17: Reinterpret block parameters dialog box Parameters specific to the block are: • Force Arithmetic Type : When checked, the Output Arithmetic Type parameter can be set and the output type will be forced to the arithmetic typechos...

44 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The following waveform illustrates the block’s behavior: Figure 3-18: Example of Serial to Parallel behavior This example illustrates the case where the input width is 1, output width is 4, wordsize is 1 bit, and the block is ...

Basic Elements 45 Xilinx Blocks • Binary Point : Output binary point location Other parameters used by this block are explained in the Common Parameters sectionof the previous chapter. The Parallel to Serial block does not use a Xilinx LogiCORE. An error is reported when the number of output bits ca...

Basic Elements 47 Xilinx Blocks Figure 3-22: Slice block parameters dialog box showing different options Parameters specific to the block are: • Specify Range As : (Two Bit Locations | Upper Bit Location + Width |Lower Bit Location + Width). Allows the user to specify either the bit locations of bot...

48 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The following diagram illustrates the operation of this block. Figure 3-23: Sync block use This diagram shows a two-channel Xilinx Sync Block connected to two signal sources,with one producing a sawtooth wave and the other a s...

Basic Elements 49 Xilinx Blocks It is instructive to note that the following model produces behavior identical to theone with the Sync block. This one, though, requires the designer to examine the twoupstream pipelined sources and to insert the correct delay line length to balance thetwo pipelines. ...

50 Xilinx Development System Xilinx System Generator v2.1 Reference Guide added to the channel that is last to present a valid input sample. Note that if thisparameter is zero, the block has a feed-through path; otherwise, it does not. Other parameters used by this block are described in the Common ...

Basic Elements 51 Xilinx Blocks from din to dout. Whenever possible, put a register or delay block after an up sampleblock. Figure 3-28: Example of up sample block behavior with zero padding Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in you...

52 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Communication The blocks in the Communication library implement functions used in digitalcommunications systems, including convolutional and block channel coding,interleaving, and utility functions. Convolutional Encoder The X...

Communication 53 Xilinx Blocks Block Parameters Dialog Box The following figure shows the block parameters dialog box. Figure 3-31: Convolutional encoder block parameters dialog box Parameters specific to the block are: • Output Rate : 2 or 3. Number of output bits generated per input bit. A rate 1/...

54 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Depuncture The Xilinx Depuncture block allows you to insert arbitrary symbol intoyour input data at the location specified by the depuncture code andcreates a new value. This value is presented as output from the block.The Xil...

Communication 55 Xilinx Blocks Block Parameters Dialog Box The Xilinx depuncture block can be configured using its Block Parameters dialog box. Figure 3-33: Depuncture block parameters dialog box Parameters specific to the Xilinx Puncture block are: • Depuncture Code : specifies the depuncture patte...

58 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\sid_v1_1\doc\sid .pdf This is a licensed core, available for purchase on the Xilinx web site at: http://www.xilinx.com/ipcent...

Communication 59 Xilinx Blocks Block Parameters Dialog Box The Xilinx puncture block can be configured using its Block Parameters dialog box. Figure 3-38: Puncture block parameters dialog box Parameters specific to the Xilinx Puncture block are: • Puncture Code : specifies the puncture pattern for r...

Communication 61 Xilinx Blocks Block Parameters Dialog Box The RS Decoder block can be configured using its Block Parameters dialog box. Figure 3-40: Reed-Solomon Decoder block parameters dialog box Parameters specific to the RS Decoder block are: • Code Specification : specifies the type of RS Deco...

62 Xilinx Development System Xilinx System Generator v2.1 Reference Guide ♦ IESS-308 (208): implements IESS-308 specification (208, 192) shortened RScode. ♦ IESS-308 (219): implements IESS-308 specification (219, 201) shortened RScode. ♦ IESS-308 (225): implements IESS-308 specification (225, 205) s...

Communication 63 Xilinx Blocks • Scaling Factor : Scaling factor for the generator polynomial root index. Normally h is 1; however, it can be any positive integer between 1 and (2 16 -1). • Provide Start Pin : when checked, the block has optional start input pin. • Enable Erasure Decoding : when che...

64 Xilinx Development System Xilinx System Generator v2.1 Reference Guide type of errors that can be corrected depends on the characteristics of the Reed-Solomon code. Reed-Solomon codes are a subset of BCH (Bose, Chaudhuri, and Hocquenghem)codes and are linear block codes. A Reed-Solomon code is sp...

66 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The RS Encoder block can be configured using its Block Parameters dialog box. Figure 3-44: Reed-Solomon Encoder block parameters dialog box Parameters specific to the RS Encoder block are: • Code Sp...

68 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Other parameters used by this block are described in the Common Parameters sectionof the previous chapter. The RS Encoder block cannot be placed in an enabled subsystem in System Generatorv2.1. See the Enabled Subsystems secti...

Communication 69 Xilinx Blocks Block Interface The Viterbi Decoder has either two or three inputports and one output port. The decoder can haveeither two or three input ports depending on theconfigurable parameter indicating encoderoutput rate. Use of hard coding requires inputdata to be 1 bit wide....

70 Xilinx Development System Xilinx System Generator v2.1 Reference Guide • Traceback Length : Length of the traceback through the Viterbi trellis. Optimal length is considered to be between 5 and 7 times the constraint length. • Convolution Code 1 : Used to decode data on input port din1 . Length o...

DSP 71 Xilinx Blocks Block Interface The CIC Block has one input and one output port. The input port can be between 1and 32 bits (inclusive). The two basic building blocks of a CIC filter are the integrator and the comb. A singleintegrator is a single-pole IIR filter with a transfer function of: H(z...

72 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The CIC Block can be configured using its Block Parameters dialog box: Figure 3-47: CIC block parameters dialog box Parameters specific to this block are: • Filter Type : Interpolator or Decimator •...

DSP 73 Xilinx Blocks DDS The Xilinx DDS Block implements a direct digital synthesizer (DDS),also commonly called a numerically controlled oscillator (NCO). Theblock employs a look-up table scheme to generate real or complexvalued sinusoids. An internal look-up table stores samplesrepresenting one pe...

74 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-49: DDS block parameters dialog box Parameters specific to the DDS block are: • Function : ...

DSP 75 Xilinx Blocks • Phase Increment Type : specifies ∆θ to be either constant or register. Choice of register activates optional ports on the block. • Phase Increment : specifies value of phase increment constant, a multiple of 2 π . The number of bits is determined in one of two ways. If the inc...

76 Xilinx Development System Xilinx System Generator v2.1 Reference Guide for k=0, 1, ... , N-1, where is a principal N-th root of unity. The FFT block accepts as input a stream of complex data represented as a pair ofXilinx fixed point data and computes successive DFTs of nonoverlapping frames of N...

DSP 77 Xilinx Blocks • Memory Usage : number of memory banks used to compute the transform, one of Single, Double, Triple (not used for 16 point FFTs). • Scale Output By : one of 1/N or 1/(2N). • Overflow characteristic : block behavior when internal overflow occurs; you may choose to invalidate the...

78 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Figure 3-52: FFT Timing Characteristics For 16-point FFTs, the block is always in the "ready for data" state and output framesare delivered continuously. Thus, there are no stall periods (stall = stall_0 = 0), and thef...

DSP 79 Xilinx Blocks The Dual Port Block Memory LogiCORE datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemdp_v3_2\do c\dp_block_mem.pdf FIR The Xilinx FIR Filter Block implements a finite-impulse response (FIR)digital filter, or a bank of identical FI...

80 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-53: FIR block parameters dialog box Parameters specific to the block are: • Coefficients : ...

Math 81 Xilinx Blocks • Polyphase behavior : Decimation, Interpolation, Single rate. • Latency : specify input sample period latency. • Hardware Over-Sampling Rate : Hardware clocks per sample. This affects hardware implementation only, and has no effect on simulation. In multi-channelmode, this fac...

82 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-54: Accumulator block parameters dialog box Parameters specific to the block are: • Number ...

Math 83 Xilinx Blocks %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\accum.pdf AddSub The Xilinx AddSub block implements an adder/subtractor.The operation can be fixed (Add or Subtract) or changeddynamically under control of the sub mode signal. Block Parameters Dialog Box The bloc...

84 Xilinx Development System Xilinx System Generator v2.1 Reference Guide uses the Xilinx LogiCORE Adder Subtractor V5.0. Otherwise, the block isimplemented as a synthesizable VHDL module. The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v...

Math 85 Xilinx Blocks saturated as needed. A positive value is implemented as an unsigned number, anegative value as signed. • Number of Bits in Constant : specifies the bit location of the binary point of the constant, where bit zero is the least significant bit. • Multiplier Type : specifies the i...

86 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-57: Inverter block parameters dialog box Parameters used by this block are explained in the...

Math 87 Xilinx Blocks Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-58: Logical block parameters dialog box Parameters specific to the block are: • Logical Function : specifies one of the following bitwise logic...

88 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Mult The Xilinx Mult block implements a multiplier. It computes theproduct of the data on its two input ports, producing the result on itsoutput port. The block supports a size-performance tradeoff in itsimplementation. It can...

Math 89 Xilinx Blocks Figure 3-60: Mult block parameters dialog box - sequential type Parameters specific to the Mult block are: • Multiplier Type : directs the implementation to be either parallel or sequential. • Require Maximum Pipelining : directs the core to be pipelined to the fullest extent p...

90 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Negate The Xilinx Negate block computes the arithmetic negation (two’scomplement) of its input. The block can be implemented either as a Xilinx LogiCORE or as asynthesizable VHDL module. Block Parameters Dialog Box The block p...

Math 91 Xilinx Blocks ♦ equal-to (a = b) ♦ not-equal-to (a != b) ♦ less-than (a < b) ♦ greater-than (a > b) ♦ less-than-or-equal-to (a <= b) ♦ greater-than-or-equal-to (a >= b) The output of the block is a 1-bit unsigned number. It is 1 if the comparison is true and0 if false. Block Para...

92 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Scale The Xilinx Scale block scales its input by a power of two. The powercan be either positive or negative. The block has one input and oneoutput. The scale operation has the effect of moving the binary pointwithout changing...

Math 93 Xilinx Blocks Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-64: Shift block parameters dialog box Parameters specific to the Shift block are: • Shift Direction : specifies a direction, Left or Right. The...

94 Xilinx Development System Xilinx System Generator v2.1 Reference Guide fundamental sinusoid lie in the half-open interval [-1, 1]. If you need a balancedrepresentation, one can be built using the Single Port RAM block with the appropriateinitialization vector. Block Parameters Dialog Box The bloc...

Math 95 Xilinx Blocks 64. This corresponds to one CLB per output bit. If the table depth is greater than 64, aquarter wave is stored, and additional logic is used to generate the remaining portionsof the wave. Storing only the quarter wave for the large tables reduces the areaneeded. Block memory st...

96 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-66: Threshold block parameters dialog box The block parameters do not control the output da...

MATLAB I/O 97 Xilinx Blocks LogiCOREs, as well as signals and control circuits to drive the clock network.Consequently, most System Generator blocks do not provide an explicit enable port.There are two exceptions> the Register block and the Addressable Shift Registerblock, which fundamentally req...

98 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-68: Gateway In block parameters dialog box Parameters specific to the Gateway In block are: • IOB Timing Constraint : I...

MATLAB I/O 99 Xilinx Blocks It should be noted there is a valid bit that accompanies the data signal. It isconstrained at the same rate. For more information concerning the valid bit, referto the Hardware Handshaking section in Chapter 1 of this manual. If Data Rate, Set 'FAST' Attribute is selected...

100 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-69: Gateway Out block parameters dialog box Parameters specific to the Gateway Out block are: • IOB Timing Constraint ...

MATLAB I/O 101 Xilinx Blocks NET "Dout<2>" FAST; NET "Dout_valid" FAST; • Specify IOB Location Constraints : Checking this option allows IOB location constraints to be specified. • IOB Pad Locations, e.g. {'Valid Bit', 'MSB', ...., 'LSB'} : IOB pin locations can be specified as...

102 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Memory This section contains Xilinx blocks that use Xilinx memory LogiCOREs. Dual Port RAM The Xilinx Dual Port RAM block implements a random accessmemory (RAM). Block Interface The block has two independent sets of ports for...

Memory 103 Xilinx Blocks by the port’s address input. During a write cycle, the user can configure the behaviorof the data out ports A/B to one of the following choices: • Read After Write • Read Before Write • No Read On Write The write modes can be described with the help of the figure below. In t...

104 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Virtex, Virtex-E and Spartan-II families support only Read After Write. Virtex-IIsupports all modes. Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model...

Memory 105 Xilinx Blocks Xilinx LogiCORE The block uses the Xilinx LogiCORE: Dual Port Block Memory v3.2 The addresswidth must be equal to where d denotes the memory depth. The tables below show the widths that are acceptable for each depth. The Core datasheet can be found on your local disk at: %XI...

106 Xilinx Development System Xilinx System Generator v2.1 Reference Guide FIFO The Xilinx FIFO block implements a First-In-First-Out memoryqueue. Values presented at the module’s data-input port is written to thenext available empty memory location when the write-enable inputis one. The memory full...

Memory 107 Xilinx Blocks • Store Only Valid Data : when checked, the block will not store any invalid data words; i.e., when the din sample is invalid, the WE (write enable) input is disregarded (if 1) and the sample is not written into the FIFO. • Zero Initial Output : when checked, initial output ...

108 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-73: ROM block parameters dialog box Parameters specific to this block are: • Depth : speci...

110 Xilinx Development System Xilinx System Generator v2.1 Reference Guide between 16 to 4096, inclusive for the other FPGA families. The word width must bebetween 1 and 1024, inclusive. The Core datasheet for the Single Port Block Memory may be found locally at: %XILINX%\coregen\ip\xilinx\eip1\com\...

Memory 111 Xilinx Blocks Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model. Figure 3-74: Single Port RAM block parameters dialog box Parameters specific to this block are: • Depth : specifies the number of words stored; must ...

112 Xilinx Development System Xilinx System Generator v2.1 Reference Guide • Read After Write • Read Before Write • No Read On Write The write modes can be described with the help of the figure shown below. In thefigure the memory has been set to an initial value of 5 and the address bit is specifie...

114 Xilinx Development System Xilinx System Generator v2.1 Reference Guide %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\do c\sp_block_mem.pdf The Core datasheet for the Distributed Memory can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\c_dist_mem_v5_0...

State Machine 115 Xilinx Blocks stream of bits. The state transition diagram and equivalent transition table are shownbelow. Figure 3-77: Mealy State Machine example transition diagram and table The table lists the next state and output that result from the current state and input.For instance, if t...

116 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The rows of the matrices correspond to the current state, and columns correspond tothe input value. The next state logic and state register in this block are implemented with high speeddedicated block RAM. The output logic is...

State Machine 117 Xilinx Blocks A block diagram of this type of state machine is shown below: Figure 3-80: Moore State Machine block diagram The block is configured by providing a next state matrix and an output array. Theyare defined by the state machine’s next state/output table. For example, cons...

118 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The Next State Matrix and the and Output Array are composed in the following way: Figure 3-82: Construction of Next State and Output matrices The rows of the matrices correspond to the current state. The next state matrix has...

State Machine 119 Xilinx Blocks Xilinx LogiCORE This block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE andVersion 5.0 of the Xilinx Distributed RAM LogiCORE. The Core datasheet for the Single Port Block Memory may be found locally at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\i...

State Machine 121 Xilinx Blocks The Registered Mealy State Machine block is configured with next state and outputmatrices obtained from the next state/output table discussed above. These matricesare constructed as follows: Figure 3-86: Construction of Next State and Output matrices The rows of the m...

122 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The number of bits used to implement a registered mealy state machine is given bythe equations: where N = total number of block RAM bits k = s = number of states i = number of input bits o = number of output bits The followin...

State Machine 123 Xilinx Blocks Registered Moore State Machine The Xilinx Registered Moore State Machine block implementsa state machine whose output depends only on the currentstate. This block is like the Moore State Machine block, exceptthat its output logic is registered. A block diagram of this...

State Machine 125 Xilinx Blocks The Next State Matrix and the Output Array are composed in the following way: Figure 3-90: Construction of Next State and Output matrices The rows of the matrices correspond to the current state. The next state matrix hasone columns for each input value. The output ar...

Using the System Generator installer 127 System Generator Software Features Chapter 4 System Generator Software Features This chapter briefly describes how to use various features of the System Generatorv2.1. It contains the following sections. • Using the System Generator installer • Using Black Bo...

128 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Installed System Generator directory The installer will create the following directory structure on your PC: These directories contain the following: • bin - This is the location of all system files. You should not add, delet...

Using Black Boxes 129 System Generator Software Features Note - For this example to run correctly, you must change your directory ( cd within the MATLAB console window) to this directory before launching the example model. The files contained in this directory are: • black_box.mdl - the Simulink mod...

130 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Use of mixed language projects System Generator v2.1 supports mixed language (VHDL and Verilog HDL) projects,as explained below. The System Generator ’s code-generation software creates VHDL code from thesystem representation...

Use of mixed language projects 131 System Generator Software Features enter information describing clocks, parameter names, types and values asappropriate. Figure 4-2: Black Box block parameters dialog box Creating mixed language synthesis and simulation projects The following describes how to synth...

132 Xilinx Development System Xilinx System Generator v2.1 Reference Guide vlog<file> line for each Verilog wrapper that is listed in the verilogFiles file, another file produced by System Generator. The vsim line in the vsim.do file needs to be augmented by adding a -L unisim suffix. Tips for...

Using the System Generator Constraints Files 133 System Generator Software Features enable or clear port may result in large fanout signals, thus degrading systemperformance. Figure 4-3: Use Global Port selections if necessary • Use cross-probing between the Xilinx Timing Analyzer and Leonardo orSyn...

134 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The division of the design into parts, and the speed at which each part must run, arespecified in the constraints file using multicycle path constraints. The example belowshows how this is done. IOB Timing and Placement Const...

136 Xilinx Development System Xilinx System Generator v2.1 Reference Guide cell array of strings in the box labeled IOB Pad Locations. Locations are package-specific; in this example a Virtex-E 2000 in a FG680 package is used. The locationconstraints for the Din bus are provided in the dialog box as...

Files automatically created by System Generator 137 System Generator Software Features Files automatically created by System Generator When a System Generator project is created, the software produces design VHDL andcores from the Xilinx CORE Generator. In addition, many other project files arecreat...

Xilinx ISE 4.1i Project Navigator 139 Using the Xilinx Software Chapter 5 Using the Xilinx Software This chapter describes how to process your System Generator design with the Xilinxdownstream software tools. Sections in this chapter are: • Xilinx ISE 4.1i Project Navigator • Using an EDIF software ...

140 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Navigator properties dialog. Right-click on the device and default package at the topof the sources window, and select Properties .. Figure 5-1: Launching Project Navigator properties dialog This will bring up the Properties ...

Xilinx ISE 4.1i Project Navigator 141 Using the Xilinx Software In the Sources window, select the top-level VHDL module in your design. Now youwill notice that the Process window shows you all available processes that can be runon the top-level VHDL module. Figure 5-3: Processes available to VHDL de...

142 Xilinx Development System Xilinx System Generator v2.1 Reference Guide • pn_posttranslate.do - this file will run a simulation on the output of the Xilinx translation (ngdbuild) step, the first step of implementation. • pn_postmap.do - to run a simulation after your design has been mapped. This ...

Using an EDIF software flow 143 Using the Xilinx Software were generated in Simulink. Provided that your design was error free, the ModelSimconsole window will report that the simulation finished without errors. Your installed version of ModelSim (either MXE or ModelSim EE/SE/PE) must beassociated w...

144 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Xilinx supplies two sets of instructions for compiling your IP libraries using TCL/TKscripts. The instructions can be found at the following locations: http://support.xilinx.com/techdocs/2561.htm http://support.xilinx.com/tec...

Xilinx software tools resources 145 Using the Xilinx Software After you make this association, your System Generator projects within ProjectNavigator will automatically use this ModelSim simulator. Figure 5-10: Processes associated with System Generator testbench in ProjectNavigator Xilinx software ...

146 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Chapter 6 Auxiliary Files Demonstration designs Several demonstration designs have been created and installed with the SystemGenerator software. These designs show the capabilities of the System Generatorsoftware and the Xili...

Perl scripts 147 Auxiliary Files You can also launch the MATLAB Demos window from the MATLAB console bytyping: >> demo Perl scripts As a convenience, several Perl scripts are delivered together with the SystemGenerator software. These Perl scripts generate project files or scripts that support...