Xilinx EDK 8.2i - Manual

Xilinx EDK 8.2i

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Table of Contents:

  • Page 3 – Date
  • Page 5 – Preface: About This Guide
  • Page 6 – Chapter 3: MicroBlaze Application Binary Interface
  • Page 7 – Preface; About This Guide; Manual Contents; Resource
  • Page 8 – Conventions; Typographical; Courier font; Courier bold; Italic font
  • Page 9 – Online Document; allow block block_name
  • Page 11 – Chapter 1; MicroBlaze Architecture; Overview; shows a functional block diagram of the MicroBlaze core.; Features; The processor ’s fixed feature set includes:; MicroBlaze Core Block Diagram
  • Page 12 – Chapter 1: MicroBlaze Architecture; Configurable Feature Overview by MicroBlaze Version
  • Page 13 – Data Types and Endianness; Chapter 4, “MicroBlaze Instruction; Word Data Type
  • Page 14 – Instruction Set Nomenclature; x bit immediate value
  • Page 15 – op1 if cond else op2
  • Page 16 – Type A
  • Page 17 – Instructions; MicroBlaze Instruction Set Summary (Continued)
  • Page 20 – Registers
  • Page 21 – General Purpose Registers; Please refer to; Special Purpose Registers; Bits; 2-bit general purpose register
  • Page 22 – PC
  • Page 24 – EAR
  • Page 25 – Exception in delay slot.
  • Page 26 – Store Access Exception; Source/Destination Register
  • Page 31 – Pipeline Architecture
  • Page 32 – Branches; Delay Slots; Memory Architecture; For details on the different memory interfaces please refer to
  • Page 33 – Vectors and Return Address Register File Location
  • Page 34 – Reset; Equivalent Pseudocode; Hardware Exceptions; Exception Causes
  • Page 35 – Breaks; Hardware Breaks
  • Page 36 – Interrupt
  • Page 37 – Instruction Cache; Instruction Cache Organization
  • Page 38 – Instruction Cache Operation; MSR Bit; Chapter 4, “MicroBlaze Instruction Set Architecture”; Data Cache; The data cache has the following features
  • Page 39 – General Data Cache Functionality; Data Cache Organization
  • Page 40 – Data Cache Software Support; The contents of the cache is preserved when the cache is disabled.; WDC Instruction; The MicroBlaze floating point unit is based on the
  • Page 41 – Format; -bit biased exponent; Rounding; “General Purpose Registers”; Arithmetic; The FPU implements the following floating point operations:; IEEE 754 Single Precision format
  • Page 42 – Comparison; The FPU implements the following floating point comparisons:; Exceptions; get; Hardware Acceleration using FSL
  • Page 43 – Debug and Trace; Debug Overview; Support for multiple processors; Trace Overview; MicroBlaze; FSLx; FSLx
  • Page 45 – Chapter 2; MicroBlaze Signal Interface Description; MicroBlaze I/O Overview
  • Page 46 – Chapter 2: MicroBlaze Signal Interface Description; Summary of MicroBlaze Core I/O
  • Page 48 – Signal
  • Page 49 – Local Memory Bus (LMB) Interface Description; LMB Signal Interface; not used
  • Page 50 – AS; Byte Lanes Used
  • Page 51 – LMB Transactions; Generic Write Operation; LMB Generic Write Operation
  • Page 52 – LMB Single Cycle Back-to-Back Read Operation
  • Page 53 – Read and Write Data Steering
  • Page 54 – Fast Simplex Link (FSL) Interface Description; Master FSL Signal Interface
  • Page 55 – FSL Transactions; FSL BUS Write Operation; Xilinx CacheLink (XCL) Interface Description; cache used in this example); Memory; Schematic
  • Page 56 – CacheLink Signal Interface; MicroBlaze Cache Link signals
  • Page 57 – CacheLink Transactions
  • Page 58 – Instruction Cache Read Miss; Data Cache Read Miss; Write the word aligned; Data Cache Write
  • Page 59 – Debug Interface Description
  • Page 60 – MicroBlaze Trace signals
  • Page 61 – MicroBlaze Core Configurability
  • Page 65 – Chapter 3; Scope; Data types in MicroBlaze assembly programs
  • Page 66 – Register Usage Conventions; Register usage conventions
  • Page 67 – “MicroBlaze Application Binary Interface”; Stack Convention
  • Page 69 – Calling Convention; Refer to; Memory Model; Small data area
  • Page 70 – Interrupt and Exception Handling; Code for passing control to exception and interrupt handlers
  • Page 71 – Chapter 4; MicroBlaze Instruction Set Architecture; Summary; Symbol notation; rx
  • Page 72 – Chapter 4: MicroBlaze Instruction Set Architecture; Formats
  • Page 73 – Arithmetic Add; Description; Registers Altered; rD; Latency; cycle; Note; add
  • Page 74 – Arithmetic Add Immediate; Notes; addi
  • Page 75 – Logical AND; and
  • Page 76 – Logial AND with Immediate; andi
  • Page 77 – Logical AND NOT; andn
  • Page 78 – Logical AND NOT with Immediate; andni
  • Page 79 – Branch if Equal; beq; Branch if Equal; beqd; Branch if Equal with Delay
  • Page 80 – Branch Immediate if Equal; Branch Immediate if Equal; beqid; Branch Immediate if Equal with Delay
  • Page 81 – Branch if Greater or Equal; Branch if Greater or Equal; bged; Branch if Greater or Equal with Delay
  • Page 82 – Branch Immediate if Greater or Equal; Branch Immediate if Greater or Equal; bgeid; Branch Immediate if Greater or Equal with Delay
  • Page 83 – Branch if Greater Than; Branch if Greater Than; bgtd; Branch if Greater Than with Delay
  • Page 84 – Branch Immediate if Greater Than; Branch Immediate if Greater Than; bgtid; Branch Immediate if Greater Than with Delay
  • Page 85 – Branch if Less or Equal; Branch if Less or Equal; bled; Branch if Less or Equal with Delay
  • Page 86 – Branch Immediate if Less or Equal; Branch Immediate if Less or Equal; bleid; Branch Immediate if Less or Equal with Delay
  • Page 87 – Branch if Less Than; Branch if Less Than; bltd; Branch if Less Than with Delay
  • Page 88 – Branch Immediate if Less Than; Branch Immediate if Less Than; bltid; Branch Immediate if Less Than with Delay
  • Page 89 – Branch if Not Equal; bne; Branch if Not Equal; bned; Branch if Not Equal with Delay
  • Page 90 – Branch Immediate if Not Equal; Branch Immediate if Not Equal; bneid; Branch Immediate if Not Equal with Delay
  • Page 91 – br; Unconditional Branch; Branch to the instruction located at address determined by rB.; Pseudocode
  • Page 92 – The instructions brl and bral are not available.
  • Page 93 – bri; Unconditional Branch Immediate
  • Page 94 – The instructions brli and brali are not available.
  • Page 95 – Break; cycles; brk
  • Page 96 – Break Immediate; brki
  • Page 97 – Barrel Shift; bsrl; Barrel Shift Right Logical; bsra; Barrel Shift Right Arithmetical; bsll; Barrel Shift Left Logical
  • Page 98 – bsi; Barrel Shift Immediate; bsrli; Barrel Shift Right Logical Immediate; bsrai; Barrel Shift Right Arithmetical Immediate; bslli; Barrel Shift Left Logical Immediate
  • Page 99 – Integer Compare; cmp
  • Page 100 – Floating Point Arithmetic Add; cycles; fadd
  • Page 101 – Reverse Floating Point Arithmetic Subtraction; frsub
  • Page 102 – Floating Point Arithmetic Multiplication; fmul
  • Page 103 – Floating Point Arithmetic Division; fdiv
  • Page 104 – fcmp; Floating Point Number Comparison; OpSel; Floating Point Comparison Operation
  • Page 106 – get from fsl interface; The get instruction has four variants.
  • Page 107 – Integer Divide; idiv
  • Page 108 – Immediate; imm; IMM
  • Page 109 – Load Byte Unsigned; lbu
  • Page 110 – Load Byte Unsigned Immediate; lbui
  • Page 111 – Load Halfword Unsigned; lhu
  • Page 112 – Load Halfword Unsigned Immediate; lhui
  • Page 113 – Load Word; lw
  • Page 114 – Load Word Immediate; lwi
  • Page 115 – Move From Special Purpose Register; mfs
  • Page 116 – Read MSR and clear bits in MSR; The immediate values has to be less than 2; msrclr
  • Page 117 – Read MSR and set bits in MSR; msrset
  • Page 118 – Move To Special Purpose Register; Copies the contents of register rD into the MSR or FSR.; rS; The PC, ESR and EAR cannot be written by the MTS instruction.; mts
  • Page 119 – Multiply; mul
  • Page 120 – Multiply Immediate; muli
  • Page 121 – Logical OR; or
  • Page 122 – Logical OR with Immediate; ori
  • Page 123 – Pattern Compare Byte Find; If none of the byte pairs match, rD is set to 0; pcmpbf
  • Page 124 – Pattern Compare Equal; rD is loaded with 1 if they match, and 0 if not; pcmpeq
  • Page 125 – Pattern Compare Not Equal; rD is loaded with 0 if they match, and 1 if not; pcmpne
  • Page 126 – put to fsl interface; The put instruction has four variants.; put
  • Page 127 – Arithmetic Reverse Subtract; rsub
  • Page 128 – rsubi; Arithmetic Reverse Subtract Immediate; When the Carry is set by a subtraction, it means that
  • Page 129 – Return from Break; cycles; Convention is to use general purpose register r16 as rA.; rtbd
  • Page 130 – Return from Interrupt; Convention is to use general purpose register r14 as rA.; rtid
  • Page 131 – Return from Exception; rted
  • Page 132 – Return from Subroutine; Convention is to use general purpose register r15 as rA.; rtsd
  • Page 133 – Store Byte; None; sb
  • Page 134 – Store Byte Immediate; sbi
  • Page 135 – Sign Extend Halfword
  • Page 137 – Store Halfword; sh
  • Page 138 – Store Halfword Immediate; shi
  • Page 139 – Shift Right Arithmetic; sra
  • Page 140 – Shift Right with Carry; src
  • Page 141 – Shift Right Logical; srl
  • Page 142 – Store Word; sw
  • Page 143 – Store Word Immediate; Register Altered; swi
  • Page 144 – Write to Data Cache; wdc
  • Page 145 – Write to Instruction Cache; wic
  • Page 146 – Logical Exclusive OR; xor
  • Page 147 – Logical Exclusive OR with Immediate; xori
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MicroBlaze
Processor
Reference Guide

Embedded Development Kit
EDK 8.2i

UG081 (v6.0) June 1, 2006

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Summary

Page 3 - Date

UG081 (v6.0) June 1, 2006 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 MicroBlaze Processor Reference GuideUG081 (v6.0) June 1, 2006 The following table shows the revision history for this document. Date Version Revision 10/01/02 1.0 Xilinx EDK 3.1 release 03/11/03 2.0 Xilinx E...

Page 5 - Preface: About This Guide

UG081 (v6.0) June 1, 2006 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 Preface: About This Guide Manual Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources . . . . . . . . . . ...

Page 6 - Chapter 3: MicroBlaze Application Binary Interface

UG081 (v6.0) June 1, 2006 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MicroBlaze I/O Overview . . . . . . . . . . . . . . . . . . . . ....

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