Xilinx UG144 - Manual

Xilinx UG144

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Table of Contents:

  • Page 3 – Revision History
  • Page 5 – Table of Contents
  • Page 9 – Schedule of Figures
  • Page 13 – Schedule of Tables
  • Page 15 – Preface; About This Guide; Guide Contents
  • Page 16 – Conventions; Typographical
  • Page 17 – The following table describes acronyms used in this manual.
  • Page 19 – Chapter 1; Introduction; About the Core; Recommended Design Experience; Related Xilinx Ethernet Products and Services
  • Page 20 – Specifications; Feedback; GEMAC Core
  • Page 21 – Chapter 2; Core Architecture; System Overview
  • Page 22 – Core Components
  • Page 23 – Core Interfaces; GMAC Core with Optional Management Interface
  • Page 24 – GMAC Core Without Management Interface and With Address Filter
  • Page 26 – Transmitter Interface
  • Page 27 – Receiver Interface; Flow Control Interface
  • Page 29 – Asynchronous Reset; Physical Side Interface; GMII
  • Page 31 – Chapter 3; Generating the Core; Graphical User Interface
  • Page 32 – Component Name; Address Filter; Number of Address Table Entries; Parameter Values in the XCO File
  • Page 33 – Output Generation
  • Page 35 – Chapter 4; Designing with the Core; General Design Guidelines; Design Steps; Using the Example Design as a Starting Point
  • Page 37 – Implementing the 1-Gigabit Ethernet MAC in Your Application; Know the Degree of Difficulty
  • Page 38 – Keep it Registered; Use Supported Design Flows
  • Page 39 – Chapter 5; Using the Client Side Data Path; Receiving Inbound Frames; Normal Frame Reception
  • Page 41 – Frame Reception with Errors
  • Page 42 – Client-Supplied FCS Passing; VLAN Tagged Frames
  • Page 43 – Maximum Permitted Frame Length; Length/Type Field Error Checks; Enabled; Disabled
  • Page 47 – Transmitting Outbound Frames; Normal Frame Transmission; Padding
  • Page 48 – Client Underrun
  • Page 49 – Inter-Frame Gap Adjustment
  • Page 50 – Transmitter Statistics Vector
  • Page 53 – Chapter 6; Using Flow Control; Overview of Flow Control; Flow Control Requirement
  • Page 54 – Flow Control Basics
  • Page 55 – Pause Control Frames
  • Page 56 – Flow Control Operation of the GEMAC; Transmitting a PAUSE Control Frame; Core-initiated Pause Request; Client Initiated Pause Request
  • Page 57 – Receiving a Pause Control Frame; Core Initiated Response to a Pause Request; Pause Frame Reception Disabled; Client Initiated Response to a Pause Request
  • Page 58 – Flow Control Implementation Example; Method
  • Page 59 – Operation; time
  • Page 61 – Chapter 7; Using the Physical Side Interface; Implementing External GMII; GMII Transmitter Logic
  • Page 63 – GMII Receiver Logic
  • Page 64 – DCM Reset circuitry
  • Page 66 – Implementing External RGMII; RGMII Transmitter Logic
  • Page 70 – RGMII Receiver Logic
  • Page 76 – Using the MDIO interface; Connecting the MDIO to an Internally Integrated PHY; Connecting the MDIO to an External PHY
  • Page 77 – Chapter 8; Configuration and Status; Using the Optional Management Interface; Host Clock Frequency
  • Page 79 – Receiver Configuration
  • Page 80 – Transmitter Configuration
  • Page 81 – Flow Control Configuration
  • Page 83 – Writing and Reading to and from the Configuration Registers
  • Page 85 – Accessing the Address Table
  • Page 86 – Introduction to MDIO
  • Page 87 – Abbreviations Used; Write Transaction
  • Page 88 – Read Transaction
  • Page 90 – Access without the Management Interface
  • Page 93 – Chapter 9; Constraining the Core; Required Constraints; Device, Package, and Speedgrade Selection
  • Page 94 – PERIOD Constraints for Clock Nets; MDIO Logic
  • Page 95 – Timespecs for Critical Logic within the Core; Flow Control
  • Page 96 – Timespecs for Reset Logic within the Core; Constraints when Implementing an External GMII; GMII IOB Constraints
  • Page 97 – GMII Input Setup/Hold Timing
  • Page 99 – Understanding Timing Reports for GMII Setup/Hold Timing; Virtex-5 devices with Delayed Data/Control
  • Page 100 – Virtex-5 Devices with Delayed Clock
  • Page 101 – Constraints when Implementing an External RGMII; RGMII IOB Constraints
  • Page 102 – RGMII Input Setup/Hold Timing
  • Page 104 – RGMII DDR Constraints
  • Page 105 – Understanding Timing Reports for RGMII Setup/Hold timing; Virtex-5 devices with delayed Data/Control
  • Page 109 – Clocking and Resetting; Clocking the Core; With Internal GMII; With External GMII
  • Page 110 – With RGMII; Standard Clocking Scheme; Multiple Cores
  • Page 112 – Reset Conditions
  • Page 113 – Interfacing to Other Cores; Ethernet 1000Base-X PCS/PMA or SGMII Core
  • Page 114 – Integration to Provide 1000BASE-X PCS with TBI
  • Page 117 – Virtex-5 LXT and SXT Devices
  • Page 119 – Integration to Provide SGMII Functionality; Ethernet Statistics Core
  • Page 123 – Implementing Your Design; Pre-implementation Simulation; Using the Simulation Model; Synthesis; XST—VHDL
  • Page 124 – XST—Verilog; Implementation; Generating the Xilinx Netlist
  • Page 125 – Static Timing Analysis; Generating a Bitstream; Post-Implementation Simulation; Generating a Simulation Model
  • Page 126 – Using the Model; Other Implementation Information
  • Page 127 – Appendix A; Using the Client-Side FIFO
  • Page 128 – Interfaces; Transmit FIFO
  • Page 129 – Receive FIFO
  • Page 130 – Overview of LocalLink Interface; Data Flow
  • Page 131 – Functional Operation; Clock Requirements
  • Page 132 – Verilog; Expanding Maximum Frame Size
  • Page 133 – Appendix B; Verification by Simulation
  • Page 135 – Appendix C; Calculating DCM Phase-Shifting; Finding the Ideal Phase-Shift
  • Page 137 – Appendix D; Core Latency; Transmit Path Latency
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LogiCORE™ IP
1-Gigabit Ethernet
MAC v8.5

User Guide

UG144 April 24, 2009

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Summary

Page 3 - Revision History

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009 -- DISCONTINUED PRODUCT -- Revision History The following table shows the revision history for this document. Date Version Revision 09/30/04 1.0 Initial Xilinx release. 04/28/05 2.0 Updated to 1-Gigabit Ethernet MAC version 6...

Page 5 - Table of Contents

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009 -- DISCONTINUED PRODUCT -- Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Schedule of Tables . . . . . . . . . . . . . . . . . . . . ....

Page 9 - Schedule of Figures

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 9 UG144 April 24, 2009 -- DISCONTINUED PRODUCT -- Chapter 1: Introduction Chapter 2: Core Architecture Figure 2-1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 2...

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