Xilinx PCI32 - Manual
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Table of Contents:
- Page 2 – Fact Table Notes; Core Implementation
- Page 3 – Notes; Applications; • Hot swap CompactPCI boards; General Description; Spartan
- Page 4 – Functional Description
- Page 5 – Figure 1; PCI I/O Interface Block; Table 2; Parity Generator/Checker; PCI Local Bus Specification
- Page 6 – Target State Machine; Interface Configuration; Device and vendor ID; Burst Transfer; Table 3
- Page 8 – Timing Specifications; Table 4; Command
- Page 9 – Timing Parameters, 66 MHz Implementations; Symbol; Timing Parameters, 33 MHz Implementations
- Page 10 – Ordering Information; Build; IP Center; Part Numbers; - Access to the v3.0 PCI32 33 MHz Spartan and 66 MHz Virtex Families
- Page 11 – Revision History; The following table shows the revision history for this document.; Date; Style updates
DS206 August 31, 2005
1
Product Specification v3.0.151
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective
owners. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx
makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly
disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from
claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
co.
com
Features
• Fully PCI 3.0-compliant LogiCORE™, 32-bit, 66/33
MHz interface
• Customizable, programmable, single-chip solution
• Pre-defined implementation for predictable timing
• Incorporates Xilinx Smart-IP™ technology
• 3.3V operation at 0-66 MHz
• 5.0V operation at 0-33 MHz
• Fully verified design tested with Xilinx proprietary
testbench and hardware
• Available through the Xilinx CORE Generator™
v7.1i or higher
• CardBus compliant
• Supported initiator functions:
- Configuration read, configuration write
- Memory read, memory write, MRM, MRL
- Interrupt acknowledge, special cycles
- I/O read, I/O write
• Supported target functions:
- Type 0 configuration space header
- Up to three base address registers (MEM or I/O
with adjustable block size from 16 bytes to 2 GB)
- Medium decode speed
- Parity generation, parity error detection
- Configuration read, configuration write
- Memory read, memory write, MRM, MRL
- Interrupt acknowledge
- I/O read, I/O write
- Target abort, target retry, target disconnect
0
PCI32 Interface v3.0
DS206 August 31, 2005
0
0
Product Specification v3.0.151
LogiCORE Facts
PCI32 Resource Utilization
(1)
Slice Four Input LUTs
553
Slice Flip-Flops
566
IOB Flip-Flops
97
IOBs
50
TBUFs
288
GCLKs
1
(2)
Provided with Core
Documentation
PCI32 Product Specification
PCI Getting Started Guide
PCI User Guide
Design File Formats
Verilog/VHDL Simulation Model
NGO Netlist
Constraints Files
User Constraints File (UCF)
Guide File (NCD)
Example Design
Verilog/VHDL Example Design
Design Tool Requirements
Xilinx Tools
v7.1i Service Pack
4
Tested Entry and
Verification Tools
(3)
Synplicity Synplify
Xilinx XST
(4)
Model Technology ModelSim
Exemplar LeonardoSpectrum
Cadence NC-Verilog
Xilinx provides technical support for this LogiCORE product when
used as described in the
PCI Getting Started Guide
and
PCI User
Guide
. Xilinx cannot guarantee timing, functionality, or support of
product if implemented in devices not listed, or if customized
beyond that allowed in the product documentation.
"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.
Summary
PCI32 Interface v3.0 2 www.xilinx.com DS206 August 31, 2005 Product Specification v3.0.151 Fact Table Notes 1. Resource utilization depends on configuration of the interface and user design. Unused resources are trimmed by the Xilinx technology mapper. The utilization figures reported in this table ...
PCI32 Interface v3.0 DS206 August 31, 2005 www.xilinx.com 3 Product Specification v3.0.151 Notes 1. Spartan-3 and Spartan-3E solution pending production speed files.2. For additional Part/Package combinations, see the UCF Generator in the PCI Lounge.3. XC2V1000 is supported over Military Temp. range...
PCI32 Interface v3.0 4 www.xilinx.com DS206 August 31, 2005 Product Specification v3.0.151 Other FPGA resources that can be used in conjunction with the core to enable efficient implementationof a PCI system include: • Block SelectRAM™ memory. Blocks of on-chip ultra-fast RAM with synchronous write ...
