Xilinx ML403 - Manual

Xilinx ML403

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Table of Contents:

  • Page 2 – Introduction; Figure 1; IIC Primer; Figure 2; ss
  • Page 3 – Figure 4; ve
  • Page 4 – Reference System Specifics; Figure 6; as
  • Page 5 – OPB IIC Registers; Table 2; xFFFFFFFF; Table 2: OPB IIC Registers; Name; Reserved
  • Page 6 – Table 4; . This bit must be set if arbitration is lost or if a transmit error; Table 4: Status Register Bit Definitions
  • Page 7 – Table 5
  • Page 8 – Configuring the OPB IIC Core; Figure 8
  • Page 9 – ML403 Board Information; Figure 10: 24LC04 Control Byte Allocation; Figure 11: ML40x Schematic for IIC Connections; CL
  • Page 10 – The resistors are located on the board as shown in
  • Page 11 – The resistor values are dependent on the voltage.
  • Page 12 – shows the FPGA pins driving the IIC Bus.; TotalPhase Aardvark Adapter; Figure 14: FPGA IIC Pins
  • Page 13 – shows the Aardvark Control Center GUI.
  • Page 14 – Executing the Reference System from EDK; Generate Bitstream to generate a bitstream; Software Projects; src; Projects interfacing to Microchip 24LC04
  • Page 15 – Projects interfacing to Aardvark Adapter; shows the repeated start example.
  • Page 16 – Running the Applications; shows the structure of the
  • Page 17 – From XPS, start XMD and enter; rst; shown in
  • Page 18 – Figure 22: ChipScope Inserter Setup
  • Page 19 – intr; Figure 23: Making Net Connections in ChipScope Inserter
  • Page 20 – Using ChipScope with OPB IIC; As shown in
  • Page 21 – vcd2wlf; Linux Kernel; Add; To generate the Linux LSP in XPS, enter Software; Figure 25: ChipScope Analyzer Results
  • Page 22 – Figure 26: BSP Settings
  • Page 23 – make oldconfig; make menuconfig; Figure 27: Connected Peripherals
  • Page 24 – Simulation; Open
  • Page 25 – Internal signal names used in the OPB IIC core are provided in; BFM
  • Page 26 – The simulation runs for 2000 ns as shown in
  • Page 27 – In the first test, which is shown in
  • Page 28 – Figure 31: Arbitration Lost Test Code
  • Page 29 – The second test, shown in
  • Page 30 – Figure 33: Test code with iic_AA as Master
  • Page 31 – shows the third test shown in
  • Page 32 – provides the test code for simulation with IIC_AA as master.
  • Page 33 – References; XAPP765 Getting Started with EDK and MontaVista Linux; Initial Xilinx release.
Loading the manual

XAPP979 (v1.0) February 26, 2007

www.xilinx.com

1

© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at

http://www.xilinx.com/legal.htm

. PowerPC is

a trademark of IBM Inc. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

Summary

This application note describes how to build a reference system for the On-Chip Peripheral Bus
Inter IC (OPB IIC) core using the IBM PowerPC™ 405 Processor (PPC405) based embedded
system in the ML403 Embedded Development Platform. The reference system is Base System
Builder (BSB) based.

An IIC primer is given and an OPB IIC register reference is provided. The Xilinx Microprocessor
Debugger (XMD) commands are used for verifying that the OPB IIC core operates correctly.
Several software projects illustrate how to configure the OPB IIC core, set up interrupts, and do
read and write operations. Some of the software projects interface the OPB IIC to the
MicroChip 24LC04B serial EEPROM with an IIC interface, while others interface to the
TotalPhase Aardvark Adapter, which provides IIC master and slave functionality. The procedure
for using ChipScope™ to analyze OPB IIC functionality is provided. The steps used to build a
Linux kernel using MontaVista are listed. Simulation output files for analyzing basic IIC
transactions are provided.

Included
Systems

This application note includes one reference system:

www.xilinx.com/bvdocs/appnotes/xapp979.zip

The project name used in xapp979.zip is ml403_ppc_opb_iic.

Required
Hardware/Tools

Users must have the following tools, cables, peripherals, and licenses available and installed:

•

Xilinx EDK 8.2.02i

•

Xilinx ISE 8.2.03

•

Xilinx Download Cable (Platform Cable USB or Parallel Cable IV)

•

Monta Vista Linux v2.4 Development Kit

•

Modeltech ModelSim v6.1d

•

ChipScope v8.2

Application Note: Embedded Processing

XAPP979 (v1.0) February 26, 2007

Reference System: OPB IIC Using the
ML403 Evaluation Platform

Author: Paul Glover, Ed Meinelt, Lester Sanders

R

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Summary

Page 2 - Introduction; Figure 1; IIC Primer; Figure 2; ss

Introduction XAPP979 (v1.0) February 26, 2007 www.xilinx.com 2 R Introduction This application note accompanies a reference system built on the ML403 development board. Figure 1 is a block diagram of the reference system. The system uses the embedded PowerPC (PPC) as the microprocessor and the OPB I...

Page 3 - Figure 4; ve

Introduction XAPP979 (v1.0) February 26, 2007 www.xilinx.com 3 R Figure 4 shows the format of the data transfer of two bytes on the IIC bus, beginning with the START (S) condition and ending with the STOP (P) condition, bounded by an idle IIC (F) bus.After a START condition, an eight bit field is tr...

Page 4 - Reference System Specifics; Figure 6; as

Reference System Specifics XAPP979 (v1.0) February 26, 2007 www.xilinx.com 4 R Figure 6 shows the acknowledge bit on the IIC bus. Figure 7 shows bus arbitration of two masters. The IIC bus is a multi-master bus. Masters monitor the IIC bus to determine if the bus is active. The bus is inactive when ...

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