Xilinx ML605 - Manual

Xilinx ML605

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Table of Contents:

  • Page 2 – ML605 Hardware User Guide; Revision History; The following table shows the revision history for this document.
  • Page 3 – Preface: About This Guide; Table of Contents
  • Page 4 – Configuration Options; Appendix A: Default Switch and Jumper Settings
  • Page 5 – Preface; About This Guide; Guide Contents; Appendix A, “Default Switch and Jumper Settings.”; Additional Documentation
  • Page 6 – Additional Support Resources
  • Page 7 – Chapter 1; ML605 Evaluation Board; Overview; “Detailed Description,” page 11; Additional Information; Additional information and support material is located at:
  • Page 8 – Features; 28 Mb Platform Flash XL
  • Page 10 – Block Diagram; shows a high-level block diagram of the ML605 and its peripherals.; Related Xilinx Documents; Appendix D, “References”; ML605 High-Level Block Diagram
  • Page 11 – Detailed Description; shows a board photo with numbered features corresponding to; Number
  • Page 13 – References; See the; Configuration; The ML605 supports configuration in the following modes:
  • Page 14 – and; Virtex-6 FPGA Configuration Modes; Voltage Rails
  • Page 15 – The ML605 DDR3 64-bit wide interface has been tested to 800 MT/s.; U1 FPGA Bank; DDR3 SODIMM Connections
  • Page 19 – See the Micron Technology, Inc. for more information
  • Page 20 – Mb Platform Flash XL; PCI Express Card Electromechanical Specification; 2 MB Linear BPI Flash; “Configuration Options,” page 73; Platform Flash and BPI Flash Block Diagram; witch 4
  • Page 21 – ML605 Flash Boot Options; The ML605 has two parallel wired flash memory devices as shown in; Platform Flash and BPI Flash Connections
  • Page 23 – FPGA Design Considerations for the Configuration Flash; for details on the Set Configuration Register command.; See the Numonyx
  • Page 24 – System ACE CF and CompactFlash Connector; file located in the root directory. The
  • Page 25 – lists the System ACE CF connections.; System ACE CF Connections
  • Page 26 – The JTAG chain of the board is illustrated in; JTAG Chain Diagram
  • Page 30 – GTX SMA Clock; GTX SMA Clock Connections
  • Page 31 – The ML605 provides access to 20 MGTs.; MGT Clocking
  • Page 32 – PCI Express Endpoint Connectivity; is a diagram of the PCIe MGT bank 114 and 115 clocking.; IC
  • Page 34 – PCIe Edge Connector Connections
  • Page 35 – SFP Module Connector; . The SFP module connections are shown; SFP Module Control and Status; Signal
  • Page 36 – using the settings shown in; SFP Module Connections
  • Page 37 – SGMII GTX Transceiver Clock Generation; shows the connections and pin numbers for the PHY.; Board Connections for PHY Configuration Pins
  • Page 38 – See the Marvell; Ethernet PHYConnections
  • Page 39 – XPS; Refer to the; USB Type B Pin Assignments and Signal Definitions
  • Page 40 – See the Cypress; USB Controller Connections
  • Page 41 – ) supports the IIC protocol to allow the board to read the; DVI Controller Connections; U1 FPGA Pin Schematic Net Name
  • Page 44 – Kb NV Memory; The IIC memory is shown in; See the ST Micro; IIC Memory U6; IIC Memory Connections
  • Page 45 – defines the status LEDs.; Status LEDs
  • Page 46 – Ethernet PHY Status LEDs
  • Page 47 – User LEDs (8) with parallel wired GPIO male pin header; FPGA INIT and DONE LEDs; FPGA INIT B; FPGA INIT and DONE LED Connections; FPGA U1 Pin
  • Page 48 – User LEDs; The ML605 provides two groups of active-High LEDs as described in; User LEDs and GPIO Connector, Directional LEDs
  • Page 49 – User Pushbutton Switches; The ML605 provides six active-High pushbutton switches:; User LED Connections; FPGA U1 Pin Schematic Net Name GPIO J62 Pin; CPU RE
  • Page 50 – User DIP Switch; User Pushbutton Switch Connections
  • Page 51 – User SMA GPIO; ER
  • Page 52 – LCD Header Connections
  • Page 53 – Power On/Off Slide Switch SW2; CAUTION; au; PCIe
  • Page 54 – Virtex-6 FPGA Data Sheet; FPGA PROG_B Pushbutton SW4
  • Page 55 – “5. System ACE CF and CompactFlash Connector,”
  • Page 56 – Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2; DIP switch S2 is a multi-purpose selector switch (; Upper or Lower Address Select:; S2 switch 6 is used to select the upper or lower half of; Multi-Purpose Select DIP Switch S2; Configuration Mode
  • Page 58 – shows the VITA 57.1 FMC HPC connections. The connector pinout is in; VITA 57.1 FMC HPC Connections
  • Page 64 – shows the VITA 57.1 FMC LPC connections. The connector pinout is in; VITA 57.1 FMC LPC Connections
  • Page 65 – AC Adapter and Input Power Jack/Switch
  • Page 66 – Onboard Power Regulation; solutions from Texas Instruments.; ML605 Onboard Power Regulators
  • Page 67 – Onboard Power System Devices
  • Page 68 – Reference and Power Supply; illustrates the power supply and reference options on the ML605.; System Monitor External Reference
  • Page 69 – user access to the analog power supply (A; . Access to the FPGA thermal diode and dedicated analog input; core supply
  • Page 70 – ML605 Board Power Monitor; 2V Supply Monitor; Current Channel
  • Page 71 – Fan Controller
  • Page 72 – FPGA Power Supply Margining
  • Page 73 – “5. System ACE CF and CompactFlash Connector”; Mode Switch S2 Settings
  • Page 75 – Appendix A; Default Switch and Jumper Settings; Default Switch Settings; REFDES
  • Page 76 – Jumper REFDES
  • Page 77 – Appendix B; shows the pinout of the FMC LPC connector. Pins marked NC are not; FMC LPC Connector Pinout
  • Page 78 – FMC HPC Connector Pinout
  • Page 79 – Appendix C; Constraints Guide; banks. Because each user ’s FMC card
  • Page 91 – Appendix D; Documents supporting the ML605 Evaluation Board:
  • Page 92 – Additional documentation:
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Summary

Page 2 - ML605 Hardware User Guide; Revision History; The following table shows the revision history for this document.

ML605 Hardware User Guide www.xilinx.com UG534 (v1.2.1) January 21, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, ...

Page 3 - Preface: About This Guide; Table of Contents

ML605 Hardware User Guide www.xilinx.com 3 UG534 (v1.2.1) January 21, 2010 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Documentation . . . . . . . . . . . . . . . . ....

Page 4 - Configuration Options; Appendix A: Default Switch and Jumper Settings

4 www.xilinx.com ML605 Hardware User Guide UG534 (v1.2.1) January 21, 2010 FPGA_PROG_B Pushbutton SW4 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SYSACE_RESET_B Pushbutton SW3 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 System ACE CF Comp...

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