Xilinx 1000BASE-X - Manual

Xilinx 1000BASE-X

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Table of Contents:

  • Page 2 – Revision History
  • Page 3 – Table of Contents
  • Page 4 – Chapter 5: Using the Client-side GMII Data Path
  • Page 6 – Chapter 13: Interfacing to Other Cores; Chapter 14: Special Design Considerations
  • Page 9 – Schedule of Figures
  • Page 13 – Schedule of Tables
  • Page 15 – Preface; About This Guide; Guide Contents
  • Page 16 – Conventions; Typographical
  • Page 17 – Online Document
  • Page 19 – Chapter 1; Introduction; About the Core; Designs Using RocketIO Transceivers; Recommended Design Experience
  • Page 20 – Additional Core Resources; Related Xilinx Ethernet Products and Services; Technical Support; Ethernet 1000BASE-X PCS/PMA or SGMII Core
  • Page 21 – Document
  • Page 23 – Chapter 2; Core Architecture; System Overview; Ethernet 1000BASE-X PCS/PMA or SGMII Using A RocketIO Transceiver
  • Page 24 – GMII Block; Optional Auto-Negotiation Block
  • Page 25 – Optional PCS Management Registers; RocketIO Interface Block
  • Page 26 – Receiver Elastic Buffer; Core Interfaces
  • Page 31 – Client Side Interface; GMII Pinout
  • Page 33 – Common Signal Pinout
  • Page 34 – MDIO Management Interface Pinout (Optional)
  • Page 35 – Auto-Negotiation Signal Pinout
  • Page 36 – Dynamic Switching Signal Pinout; Physical Side Interface
  • Page 38 – 000BASE-X PCS with TBI Pinout
  • Page 39 – Chapter 3; Generating and Customizing the Core; GUI Interface; Component Name
  • Page 40 – Select Standard; Core Functionality
  • Page 41 – Physical Interface; MDIO Management Interface; SGMII/Dynamic Standard Switching Elastic Buffer Options
  • Page 43 – RocketIO Tile Configuration; Parameter Values in the XCO File
  • Page 44 – Output Generation
  • Page 45 – Chapter 4; Designing with the Core; Design Overview
  • Page 46 – 000BASE-X Standard Using RocketIO Transceiver Example Design
  • Page 47 – 000BASE-X Standard with TBI Example Design
  • Page 48 – SGMII Standard Using a RocketIO Transceiver Example Design
  • Page 49 – SGMII Standard with TBI Transceiver Example Design
  • Page 50 – Design Guidelines; Generate the Core; Examine the Example Design Provided with the Core
  • Page 51 – Write an HDL Application; Synthesize your Design; Simulate and Download your Design
  • Page 52 – Keep it Registered; Recognize Timing Critical Signals; Use Supported Design Flows
  • Page 53 – Using the Client-side GMII Data Path; Designing with the Client-side GMII for the 1000BASE-X Standard; GMII Transmission; Normal Frame Transmission
  • Page 54 – Error Propagation; GMII Reception; Normal Frame Reception
  • Page 55 – Normal Frame Reception with Extension Field
  • Page 56 – False Carrier; Link Synchronization
  • Page 57 – Using the Virtex-II Pro RocketIO Transceiver CRC Functionality
  • Page 59 – Designing with Client-side GMII for the SGMII Standard; Overview; Gigabit per Second Frame Transmission; 00 Megabit per Second Frame Transmission
  • Page 60 – 0 Megabit per Second Frame Transmission; Gigabit per Second Frame Reception; 00 Megabit per Second Frame Reception
  • Page 61 – 0 Megabit per Second Frame Reception; Using the GMII as an Internal Connection; Implementing External GMII; GMII Transmitter Logic
  • Page 66 – GMII Receiver Logic
  • Page 69 – Chapter 6; The Ten-Bit Interface; Transmitter Logic
  • Page 70 – Receiver Logic
  • Page 73 – Method 1
  • Page 74 – Method 2
  • Page 77 – Clock Sharing across Multiple Cores with TBI
  • Page 79 – Chapter 7; RocketIO Transceiver Logic; Virtex-II Pro Devices
  • Page 83 – Virtex-5 LXT and SXT Devices; Virtex-5 RocketIO GTP Wizard
  • Page 85 – Virtex-5 RocketIO GTX Wizard
  • Page 87 – Clock Sharing Across Multiple Cores with RocketIO
  • Page 95 – Chapter 8; Receiver Elastic Buffer Implementations; Selecting the Buffer Implementation from the GUI
  • Page 96 – The Requirement for the FPGA Fabric Rx Elastic Buffer; Analysis; FPGA
  • Page 97 – The RocketIO Rx Elastic Buffer
  • Page 98 – Closely Related Clock Sources; RocketIO Logic using the RocketIO Rx Elastic Buffer
  • Page 99 – RocketIO Logic with the Fabric Rx Elastic Buffer
  • Page 101 – Virtex-4 Devices for SGMII or Dynamic Standards Switching
  • Page 105 – Virtex-5 FXT Devices for SGMII or Dynamic Standards Switching
  • Page 115 – Chapter 9; Configuration and Status; MDIO Bus System
  • Page 116 – MDIO Transactions
  • Page 117 – Write Transaction; MDIO Addressing
  • Page 118 – Connecting the MDIO to an Internally Integrated STA
  • Page 119 – Management Registers
  • Page 120 – Register 0: Control Register
  • Page 122 – Register 1: Status Register
  • Page 124 – Register 4: Auto-Negotiation Advertisement
  • Page 125 – Register 5: Auto-Negotiation Link Partner Base
  • Page 126 – Register 7: Next Page Transmit
  • Page 127 – Register 8: Next Page Receive
  • Page 128 – Register 15: Extended Status
  • Page 129 – Register 16: Vendor-Specific Auto-Negotiation Interrupt Control; 000BASE-X Standard Without the Optional Auto-Negotiation
  • Page 133 – Registers 2 and 3: Phy Identifier
  • Page 135 – SGMII Standard Using the Optional Auto-Negotiation; Register 0: SGMII Control
  • Page 137 – Register 1: SGMII Status
  • Page 139 – Registers 2 and 3: PHY Identifier
  • Page 140 – Register 5: SGMII Auto-Negotiation Link Partner Ability
  • Page 141 – Register 6: SGMII Auto-Negotiation Expansion
  • Page 142 – Register 8: SGMII Next Page Receive
  • Page 143 – Register 15: SGMII Extended Status
  • Page 144 – Register 16: SGMII Auto-Negotiation Interrupt Control
  • Page 145 – SGMII Standard without the Optional Auto-Negotiation
  • Page 150 – Both 1000BASE-X and SGMII Standards
  • Page 151 – Register 17: Vendor-specific Standard Selection Register; Optional Configuration Vector
  • Page 153 – Overview of Operation
  • Page 155 – SGMII Standard
  • Page 156 – Setting the Configurable Link Timer; Using the Auto-Negotiation Interrupt
  • Page 157 – Typical Application
  • Page 158 – Operation of the Core; Switching the Standard Using MDIO; Auto-Negotiation State Machine
  • Page 161 – Constraining the Core; Required Constraints; Device, Package, and Speedgrade Selection
  • Page 162 – Clock Period Constraints; Setting MGT Attributes
  • Page 164 – Virtex-4 RocketIO MGTs for 1000BASE-X Constraints
  • Page 165 – Setting MGT Transceiver Attributes; MGT Placement Constraints
  • Page 166 – Virtex-5 RocketIO GTP Transceivers for 1000BASE-X Constraints; Setting GTP Transceiver Attributes
  • Page 167 – Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Constraints
  • Page 168 – Setting GTX Transceiver Attributes; Ten-Bit Interface Constraints
  • Page 169 – Ten-Bit Interface IOB Constraints
  • Page 170 – TBI Input Setup/Hold Timing; Input TBI Timing Specification
  • Page 172 – Constraints When Implementing an External GMII
  • Page 173 – GMII IOB Constraints
  • Page 174 – GMII Input Setup/Hold Timing; Input GMII timing specification
  • Page 176 – Understanding Timing Reports for Setup/Hold Timing
  • Page 179 – Interfacing to Other Cores; Integrating with the 1-Gigabit Ethernet MAC Core
  • Page 185 – Integrating with the Tri-Mode Ethernet MAC Core
  • Page 197 – Special Design Considerations; Power Management; Startup Sequencing; Loopback; Core with the TBI
  • Page 198 – Core with RocketIO Transceiver
  • Page 201 – Implementing the Design; Pre-implementation Simulation; Using the Simulation Model; Synthesis
  • Page 202 – Implementation; Generating the Xilinx Netlist
  • Page 203 – Static Timing Analysis; Post-Implementation Simulation; Generating a Simulation Model; Using the Model
  • Page 204 – Other Implementation Information
  • Page 205 – Appendix A; Verification
  • Page 207 – Appendix B; Core Latency; Latency for 1000BASE-X PCS with TBI; Transmit Path Latency
  • Page 208 – Latency for 1000BASE-X PCS and PMA Using a RocketIO Transceiver; Receive Path Latency; Latency for SGMII
  • Page 209 – Appendix C; Requirement for DCM Phase Shifting; Finding the Ideal Phase Shift Value for Your System
  • Page 211 – Appendix D
  • Page 212 – Start of Frame Encoding; The Even Transmission Case
  • Page 213 – Reception of the Even Case
  • Page 214 – Reception of the Odd Case
  • Page 215 – Preamble Shrinkage; End of Frame Encoding; The Even Transmission case
  • Page 219 – Appendix E; Rx Elastic Buffer Specifications; Rx Elastic Buffers: Depths and Maximum Frame Sizes; RocketIO Rx Elastic Buffers
  • Page 222 – SGMII Fabric Rx Elastic Buffer
  • Page 223 – TBI Rx Elastic Buffer; For SGMII / Dynamic Switching
  • Page 224 – Clock Correction
  • Page 225 – Idle Character Removal at 100 Mbps (SGMII); Idle Character Removal at 10 Mbps (SGMII)
  • Page 226 – Maximum Frame Sizes for Sustained Frame Reception; Jumbo Frame Reception
  • Page 227 – Appendix F; Debugging Guide; General Checks; Problems with the MDIO; Problems with Data Reception or Transmission
  • Page 228 – Problems with Auto-Negotiation
  • Page 229 – RocketIO Transceiver Specific; Problems with a High Bit Error Rate; Symptoms; Debugging
  • Page 230 – RocketIO Transceiver Specific Checks
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UG155 March 24, 2008

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Summary

Page 2 - Revision History

www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein, none of the Specification may be copied, reproduced, distributed, republished...

Page 3 - Table of Contents

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008 Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Page 4 - Chapter 5: Using the Client-side GMII Data Path

www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 R Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core in Your Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Chapter 5: Using the Client-side GM...

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