Xilinx UG492 - Manual

Xilinx UG492

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Table of Contents:

  • Page 2 – Revision History
  • Page 3 – Table of Contents
  • Page 4 – Chapter 4: Generating the Core
  • Page 6 – Chapter 14: Quick Start Example Design
  • Page 7 – Directory and File Contents; Appendix A: RTC Time Stamp Accuracy; Time Stamp Accuracy
  • Page 9 – Schedule of Figures
  • Page 11 – RTC Periodic Error
  • Page 13 – Schedule of Tables
  • Page 14 – Chapter 11: Constraining the Core
  • Page 17 – Preface; About This Guide; Guide Contents
  • Page 18 – Conventions; Typographical
  • Page 19 – Online Document
  • Page 20 – List of Abbreviations
  • Page 23 – Chapter 1; Introduction; System Requirements; Windows; About the Core
  • Page 24 – Recommended Design Experience; Technical Support; Ethernet AVB Endpoint Core
  • Page 25 – Feedback; Document
  • Page 27 – Chapter 2; Before you Begin; Simulation Only
  • Page 28 – Full; Obtaining Your License Key; Simulation License; Evaluate; Obtaining a Full License Key; Order; Installing the License File
  • Page 29 – Chapter 3; Example AVB Home Network
  • Page 30 – Overview of Ethernet Audio Video Bridging; Other data; AVB Specifications
  • Page 31 – Talker; Listener
  • Page 32 – Typical Implementation; Example Ethernet AVB Endpoint System
  • Page 35 – Chapter 4; Generating the Core; Ethernet AVB GUI Page 1; GUI Page 1
  • Page 36 – Component Name
  • Page 37 – Ethernet AVB GUI Page 2; Number of PLB Masters; GUI Page 2
  • Page 38 – Parameter Values in the XCO File; Output Generation; XCO File Values and Default Values
  • Page 39 – Chapter 5; Core Architecture
  • Page 40 – Standard CORE Generator Format; MAC
  • Page 41 – EDK pcore Format
  • Page 42 – Functional Block Description; PLB Interface
  • Page 43 – Tx Arbiter; Legacy Traffic; Rx Splitter; AV Traffic; MAC Header Filters
  • Page 44 – Precise Timing Protocol Blocks; Tx PTP Packet Buffers; Tx Time Stamp; Rx PTP Packet Buffers; Rx Time Stamp
  • Page 45 – RTC
  • Page 46 – Software Drivers; Tri-Mode Ethernet MACs
  • Page 47 – Core Interfaces; Clocks and Reset; Clocks and Resets
  • Page 48 – Legacy Traffic Interface; Legacy Traffic Transmitter Path Signals; Legacy Traffic Receiver Path Signals; Legacy Traffic Signals: Transmitter Path
  • Page 49 – AV Traffic Interface; AV Traffic Transmitter Path Signals; Legacy Traffic Signals: Receiver Path
  • Page 50 – AV Traffic R; Tri-Mode Ethernet MAC Client Interface; MAC Transmitter Interface; AV Traffic Signals: Receiver Path
  • Page 51 – MAC Receiver Interface; Tri-Mode Ethernet MAC Receiver Interface
  • Page 53 – PLB Signals
  • Page 55 – Interrupt Signals
  • Page 56 – PTP Signals
  • Page 57 – Chapter 6; Ethernet AVB Endpoint Transmission; Tx Legacy Traffic I/F
  • Page 58 – Error Free Legacy Frame Transmission; Normal Frame Transmission across the Legacy Traffic Interface
  • Page 59 – Errored Legacy Frame Transmission; Legacy Frame Transmission with Underrun
  • Page 60 – Normal Frame Transmission across the AV Traffic Interface
  • Page 61 – Overview; up to; Credit Based Traffic Shaping Algorithm
  • Page 62 – Credit-based Shaper Operation
  • Page 63 – Tx Arbiter Bandwidth Control; idleSlope; sendSlope
  • Page 64 – hiLimit; loLimit
  • Page 65 – Chapter 7; Ethernet AVB Endpoint Reception; Rx Legacy Traffic I/F
  • Page 66 – Error Free Legacy Frame Reception; Normal Frame Reception across the Legacy Traffic Interface
  • Page 67 – Errored Legacy Frame Reception; Legacy MAC Header Filters; Overview of Operation; Errored Frame Reception across the Legacy Traffic Interface
  • Page 68 – Normal Frame Reception: Address Filter Match
  • Page 69 – MAC Header Filter Configuration
  • Page 70 – Single MAC Header Filter Usage Examples; Filtering of Frames with a Full DA Match
  • Page 71 – Filtering of Frames with a Partial DA Match
  • Page 72 – VLAN Priority Match; Any Other Combinations; Filtering of VLAN Frames with a Specific Priority Value
  • Page 73 – Error Free AV Traffic Reception; Normal Frame Reception across the AV Traffic Interface
  • Page 74 – Errored AV Traffic Reception; Errored Frame Reception across the AV Traffic Interface
  • Page 75 – Chapter 8; Real Time Clock and Time Stamping; Real Time Clock
  • Page 77 – RTC Implementation; Increment of Nanoseconds Field; Increment of Sub-nanoseconds and Nanoseconds Field
  • Page 78 – Increment of the Seconds Field
  • Page 79 – Clock Outputs Based on the Synchronized RTC Nanoseconds Field
  • Page 80 – Time Stamp Sampling Position of MAC Frames; Time Stamping Position
  • Page 81 – IEEE1722 Real Time Clock Format
  • Page 83 – Chapter 9; Precise Timing Protocol Packet Buffers; Tx PTP Packet Buffer
  • Page 84 – Tx PTP Packet Buffer Structure
  • Page 85 – Rx PTP Packet Buffer
  • Page 87 – Configuration and Status; Processor Local Bus Interface; Single Read Transaction
  • Page 89 – Single Write Transaction
  • Page 90 – PLB Address Map and Register Definitions
  • Page 91 – PLB Address Space of the Ethernet AVB Endpoint Core and
  • Page 92 – Ethernet AVB Endpoint Address Space; Rx PTP Packet Buffer Address Space; Tx PTP Packet Buffer Address Space; Ethernet Audio Video End Point Configuration Registers; Tx PTP Packet Control Register
  • Page 93 – Rx PTP Packet Control Register; Rx Filtering Control Register
  • Page 94 – Tx Arbiter Send Slope Control Register; Tx Arbiter Idle Slope Control Register; RTC Nanoseconds Field Offset (
  • Page 95 – RTC Increment Value Control Register; Current RTC Value Registers; RTC Increment Value Control Register (
  • Page 96 – RTC Interrupt Clear Register; Current RTC Nanoseconds Value (; RTC Interrupt Clear Register (
  • Page 97 – Phase Adjustment Register; Software Reset Register; RTC Phase Adjustment Register (
  • Page 98 – MAC Header Filter Configuration Registers
  • Page 100 – Tri-Mode Ethernet MAC Address Space; MAC Configuration and Statistics; MAC Address Filter Registers; Tri-Mode Ethernet MAC and Ethernet Statistics
  • Page 101 – MAC MDIO Registers
  • Page 103 – Constraining the Core; Required Constraints; Device, Package, and Speedgrade Selection
  • Page 104 – PERIOD Constraints for Clock Nets
  • Page 105 – Timespecs for Critical Logic within the Core
  • Page 111 – System Integration; Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs
  • Page 112 – Tri-Mode Ethernet MAC Core Generation; Management Interface
  • Page 113 – Connections Without Ethernet Statistics
  • Page 115 – Connections Including Ethernet Statistics
  • Page 116 – LogiCORE IP Embedded Tri-Mode Ethernet MACs; Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper Generation; Host Type; Global Buffer Usage; Flow Control Configuration.
  • Page 117 – Connection to the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC
  • Page 118 – Core
  • Page 119 – Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC; Connection of the PLB to the EDK for LogiCORE IP Ethernet MACs
  • Page 121 – Using an EDK Project Top Level
  • Page 122 – Using an ISE Software Top-Level Project
  • Page 124 – Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC
  • Page 126 – Ethernet AVB Endpoint Connections
  • Page 127 – MHS File Syntax; Connection to the XPS LocalLink Tri-Mode Ethernet MAC
  • Page 131 – PTP Clock Master; Clock Master
  • Page 132 – Clock Slave; Software System Integration; Driver Instantiation
  • Page 133 – Interrupt Service Routine Connections
  • Page 134 – Core Initialization; When Using a LogiCORE IP Tri-Mode Ethernet MAC; Ethernet AVB Endpoint Setup
  • Page 135 – Setting up SourcePortIdentity (and Default TX PTP Messages); Setting up GrandMaster Discontinuity Callback Handler
  • Page 136 – Starting and Stopping the AVB Drivers
  • Page 137 – Quick Start Example Design
  • Page 140 – Ethernet AVB Endpoint Core Customization Screen
  • Page 141 – Implementing the Example Design; Linux; Simulating the Example Design; Setting up for Simulation; Functional Simulation
  • Page 142 – Timing Simulation
  • Page 144 – Detailed Example Design (Standard Format); Project Directory
  • Page 145 – Component Name Directory; Doc Directory; Example Design Directory
  • Page 146 – Implement Directory
  • Page 147 – Results Directory; Simulation Directory; Functional Directory
  • Page 148 – Timing Directory
  • Page 149 – Driver Example Directory
  • Page 151 – Implementation Scripts; Simulation Scripts
  • Page 152 – Example Design; Example Design HDL for the Ethernet AVB Endpoint
  • Page 153 – Top-Level Example Design HDL; Ethernet Frame Stimulus
  • Page 154 – Ethernet Frame Checker
  • Page 155 – PLB Module; Initialization; PTP Transmit Interrupt Service Routine
  • Page 156 – Demonstration Test Bench; Ethernet AVB Endpoint Demonstration Test Bench
  • Page 157 – Customizing the Test Bench; Simulation Run Time
  • Page 158 – Viewing the Simulation Wave Form; Simulator Wave Window Contents
  • Page 161 – Driver Data Directory
  • Page 162 – pcore netlist Directory
  • Page 164 – Driver Source Directory
  • Page 167 – Appendix A; RTC Time Stamp Accuracy; RTC Real Time Instantaneous Error
  • Page 169 – RTC Sampling Error; RTC Sampling Logic
  • Page 171 – Accuracy Resulting from the Combined Errors; Overall Time Stamp Accuracy
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LogiCORE

TM

IP

Ethernet AVB
Endpoint v2.4

User Guide

UG492 July 23, 2010

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Summary

Page 2 - Revision History

Ethernet AVB Endpoint User Guide www.xilinx.com UG492 July 23, 2010 Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereo...

Page 3 - Table of Contents

Ethernet AVB Endpoint User Guide www.xilinx.com 3 UG492 July 23, 2010 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Page 4 - Chapter 4: Generating the Core

4 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 4: Generating the Core Ethernet AVB GUI Page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Component Name . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

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