Xilinx Spartan-3E 1600E - Manual

Xilinx Spartan-3E 1600E

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Table of Contents:

  • Page 2 – Revision History
  • Page 3 – Preface: About This Guide; Table of Contents
  • Page 4 – Chapter 4: FPGA Configuration Options
  • Page 5 – Chapter 10: Analog Capture Circuit
  • Page 6 – Chapter 13: DDR SDRAM
  • Page 7 – Appendix A: Schematics
  • Page 9 – Preface; About This Guide; Acknowledgements
  • Page 10 – Additional Resources
  • Page 11 – Chapter 1; Introduction and Overview; Choose the Starter Kit Board for Your Needs; Spartan-3E FPGA Features and Embedded Processing Functions
  • Page 12 – Key Components and Features
  • Page 13 – Configuration Methods Galore!; Related Resources
  • Page 15 – Chapter 2; Slide Switches; Locations and Labels; UCF Location Constraints; Four Slide Switches
  • Page 16 – UCF Constraints for Slide Switches
  • Page 17 – Rotary Push-Button Switch; Input Pin; UCF Constraints for Push-Button Switches
  • Page 18 – Rotary Shaft Encoder; Pin; Basic example of rotary shaft encoder circuitry
  • Page 19 – Discrete LEDs; UCF Constraints for Rotary Push-Button Switch
  • Page 20 – Operation; Eight Discrete LEDs; UCF Constraints for Eight Discrete LEDs
  • Page 21 – Chapter 3; Clock Sources; Overview; Available Clock Inputs
  • Page 22 – Clock Inputs and Associated Global Buffers and DCMs
  • Page 23 – Location; UCF Location Constraints for Clock Sources
  • Page 25 – Chapter 4; FPGA Configuration Options
  • Page 27 – Configuration Mode Jumpers
  • Page 28 – PROG Push Button; DONE Pin LED
  • Page 29 – Programming the FPGA, CPLD, or Platform Flash PROM via USB; Connecting the USB Cable; Standard USB Type A/Type B Cable; USB Type B Connector
  • Page 30 – Programming via iMPACT; Assign New Configuration File; OK
  • Page 31 – Program; iMPACT Issues a Warning if the StartUp Clock Was Not CCLK
  • Page 32 – Programming Platform Flash PROM via USB; Generating the FPGA Configuration Bitstream File; Generator Programming File; Properties
  • Page 33 – Configuration Options; Configuration
  • Page 34 – Generate Programming File; Generating the PROM File; PROM File Formatter
  • Page 35 – Xilinx PROM; MCS; PROM File Name
  • Page 36 – Add; Finish
  • Page 37 – Enter FPGA Configuration Bitstream File(s)
  • Page 38 – Operations; PROM Formatting Completed
  • Page 39 – Programming the Platform Flash PROM; Boundary Scan
  • Page 43 – Chapter 5; Character LCD Screen; Character LCD Interface; rt
  • Page 44 – Character LCD Interface Signals; Voltage Compatibility
  • Page 45 – Interaction with Intel StrataFlash; LCD/StrataFlash Control Interaction; UCF Location Constraints for the Character LCD
  • Page 46 – LCD Controller; Memory Map; DD RAM; DD RAM Hexadecimal Addresses (No Display Shifting)
  • Page 47 – CG RAM; LCD Character Set
  • Page 48 – Command Set; Example Custom Checkerboard Character with Character Code 0x03; LCD Character Display Command Set
  • Page 49 – Disabled; Return Cursor Home
  • Page 50 – Cursor and Display Shift
  • Page 51 – Function Set; Read Busy Flag and Address; Write Data to CG RAM or DD RAM; Shift Patterns According to S/C and R/L Bits
  • Page 52 – Read Data from CG RAM or DD RAM; Four-Bit Data Interface; Character LCD Interface Timing
  • Page 53 – Transferring; Initializing the Display; Power-On Initialization
  • Page 54 – Writing Data to the Display; Disabling the Unused LCD
  • Page 55 – Chapter 6; VGA Display Port; VGA Connections from Spartan-3E Starter Kit Board
  • Page 56 – -Bit Display Color Codes
  • Page 57 – CRT Display Timing Example
  • Page 58 – VGA Signal Timing; VGA Control Timing
  • Page 59 – UCF Constraints for VGA Display Port
  • Page 61 – Chapter 7
  • Page 62 – OR
  • Page 63 – UCF Location Constraints for DTE RS-232 Serial Port
  • Page 65 – Chapter 8; PS/2 Connector Location and Signals
  • Page 66 – Keyboard; PS/2 Bus Timing Waveforms
  • Page 67 – PS/2 Keyboard Scan Codes; Common PS/2 Keyboard Commands
  • Page 68 – Mouse; PS/2 Mouse Transaction; Mo
  • Page 69 – Voltage Supply; UCF Location Constraints for PS/2 Port
  • Page 71 – Chapter 9; SPI Communication; Digital-to-Analog Converter and Associated Header
  • Page 72 – Interface Signals; Disable Other Devices on the SPI Bus to Avoid Contention; DAC Interface Signals
  • Page 73 – SPI Communication Details; Communication Protocol; Disabled Devices on the SPI Bus; SPI Communication Waveforms
  • Page 74 – Specifying the DAC Output Voltage; DAC Outputs A and B; SPI Communications Protocol to LTC2624 DAC
  • Page 75 – DAC Outputs C and D; UCF Location Constraints for the DAC Interface
  • Page 77 – Analog Capture Circuit; Two-Channel Analog Capture Circuit
  • Page 78 – Digital Outputs from Analog Inputs; Detailed View of Analog Capture Circuit
  • Page 79 – Programmable Pre-Amplifier; Interface; Programmable Gain; AMP Interface Signals
  • Page 80 – SPI Control Interface; Programmable Gain Settings for Pre-Amplifier; SPI Serial Interface to Amplifier
  • Page 82 – Detailed SPI Timing to ADC
  • Page 83 – Connecting Analog Inputs; UCF Location Constraints for the ADC Interface
  • Page 85 – Intel StrataFlash Parallel NOR Flash; Connections to Intel StrataFlash Flash Memory; as
  • Page 86 – Intel StrataFlash Parallel NOR Flash PROM; StrataFlash Connections
  • Page 89 – Shared Connections; Character LCD; SPI Data Line; FPGA Control for StrataFlash and LCD
  • Page 90 – Address; UCF Location Constraints for StrataFlash Address Inputs
  • Page 91 – Control; Setting the FPGA Mode Select Pins; UCF Location Constraints for StrataFlash Control Pins
  • Page 93 – SPI Flash Interface Signals
  • Page 94 – Configuring from SPI Flash; UCF Location Constraints for SPI Flash Connections
  • Page 95 – Creating an SPI Serial Flash PROM File; Setting the Configuration Clock Rate
  • Page 96 – Formatting an SPI Flash PROM File
  • Page 97 – Choose the PROM Target Type, the, Data Format, and File Location
  • Page 100 – Downloading the Design to SPI Flash; Downloading the SPI Flash using XSPI; Download and Install the XSPI Programming Utility; Attach a JTAG Parallel Programming Cable; PROM File Formatter Succeeded
  • Page 101 – Insert Jumper on JP; Attaching a JTAG Parallel Programming Cable to the Board
  • Page 102 – Programming the SPI Flash with the XSPI Software; xspi; Installing the JP8 Jumper Holds the FPGA in Configuration State; Programming the M25P16 SPI Flash with the XSPI Programming
  • Page 103 – Additional Design Details; Shared SPI Bus with Peripherals; Additional SPI Flash Interface Design Details; Disable Other Devices on SPI Bus
  • Page 104 – Other SPI Flash Control Signals; Jumper Block J11
  • Page 105 – Multi-Package Layout for the STMicroelectronics M25Pxx Family; VCC
  • Page 107 – DDR SDRAM; FPGA Interface to Micron 512 Mbit DDR SDRAM
  • Page 108 – DDR SDRAM Connections
  • Page 110 – UCF Location Constraints for DDR SDRAM Address Inputs
  • Page 111 – UCF Location Constraints for DDR SDRAM Control Pins
  • Page 113 – 0/100 Ethernet Physical Layer Interface
  • Page 114 – Ethernet PHY Connections; FPGA Connects to Ethernet PHY via MII
  • Page 115 – MicroBlaze Ethernet IP Cores; FPGA Connections to the LAN83C185 Ethernet PHY; Ethernet MAC IP Cores for the Spartan-3E Starter Kit Board
  • Page 116 – UCF Location Constraints for 10/100 Ethernet PHY Inputs
  • Page 117 – Expansion Connectors; Expansion Headers
  • Page 118 – Voltage Supplies to the Connector; Connector Pinout and FPGA Connections; FPGA Connections to the Hirose 100-pin Edge Connector
  • Page 119 – Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3)
  • Page 120 – Compatible Board; Mating Receptacle Connectors
  • Page 121 – Differential I/O Pairs
  • Page 122 – Using Differential Inputs; tion re
  • Page 123 – Using Differential Outputs; Location of Termination Resistor Pads on Top Side of Board
  • Page 124 – UCF Location Constraints for Accessory Headers
  • Page 125 – Six-Pin Accessory Headers; Header J1; Header J2; FPGA Connections to the J1 Accessory Header
  • Page 126 – Header J4; FPGA Connections to the J4 Accessory Header
  • Page 127 – Connectorless Debugging Port Landing Pads (J6); Connectorless Debugging Port Landing Pads (J6)
  • Page 129 – XC2C64A CoolRunner-II CPLD
  • Page 131 – FPGA Connections to CPLD; CPLD; UCF Location Constraints for FPGA Connections to CPLD
  • Page 133 – UCF Location Constraints for DS2432 SHA-1 EEPROM
  • Page 135 – Appendix A
  • Page 136 – Schematics; FX2 Expansion Header, 6-pin Headers, and Connectorless Probe
  • Page 137 – Schematic Sheet 1
  • Page 139 – Schematic Sheet 2
  • Page 141 – Schematic Sheet 4
  • Page 142 – Voltage Regulators
  • Page 144 – FPGA Configurations Settings, Platform Flash PROM, SPI Serial
  • Page 145 – Schematic Sheet 6
  • Page 147 – Schematic Sheet 7
  • Page 148 – FPGA I/O Banks 2 and 3
  • Page 150 – Power Supply Decoupling
  • Page 154 – Linear Technology ADC and DAC
  • Page 156 – Intel StrataFlash Parallel NOR Flash Memory and Micron DDR
  • Page 157 – Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM
  • Page 159 – Schematic Sheet 13
  • Page 160 – DDR SDRAM Series Termination and FX2 Connector Differential
  • Page 161 – Schematic Sheet 14
  • Page 163 – Appendix B
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MicroBlaze Development

Kit Spartan-3E 1600E

Edition User Guide

UG257 (v1.1) December 5, 2007

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Summary

Page 2 - Revision History

MicroBlaze Development Kit Spartan-3E 1600E Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007 Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as st...

Page 3 - Preface: About This Guide; Table of Contents

MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 1 UG257 (v1.1) December 5, 2007 www.xilinx.com Preface: About This Guide Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Guide Contents . . . . . . . ....

Page 4 - Chapter 4: FPGA Configuration Options

2 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007 R UCF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Location . . . . . . . . . . . . . . . . . . . . ....

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