Page 2 - SP605 Hardware User Guide; Revision History; The following table shows the revision history for this document.
SP605 Hardware User Guide www.xilinx.com UG526 (v1.1.1) February 1, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, ...
Page 3 - Preface: About This Guide; Table of Contents
SP605 Hardware User Guide www.xilinx.com 3 UG526 (v1.1.1) February 1, 2010 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Documentation . . . . . . . . . . . . . . . . ....
Page 4 - Power Management; Appendix A: Default Jumper and Switch Settings
4 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High) . . . . . . . . . . 48 Mode DIP Switch SW1 (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 18. VITA 57.1 FMC L...
Page 5 - Preface; About This Guide; Guide Contents; Appendix A, “Default Jumper and Switch Settings.”; Additional Documentation
SP605 Hardware User Guide www.xilinx.com 5 UG526 (v1.1.1) February 1, 2010 Preface About This Guide This manual accompanies the Spartan®-6 FPGA SP605 Evaluation Board and contains information about the SP605 hardware and software tools. Guide Contents This manual contains the following chapters: • C...
Page 6 - Additional Support Resources
6 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Preface: About This Guide This guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and PLLs. • Spartan-6 FPGA Block RAM Resources User Guide This guide describes the Spartan-6 device ...
Page 7 - Chapter 1; SP605 Evaluation Board; Overview; “Detailed Description,” page 10; Additional Information; Additional information and support material is located at:
SP605 Hardware User Guide www.xilinx.com 7 UG526 (v1.1.1) February 1, 2010 Chapter 1 SP605 Evaluation Board Overview The SP605 board enables hardware and software developers to create or evaluate designs targeting the Spartan®-6 XC6SLX45T-3FGG484 FPGA. The SP605 provides board features common to man...
Page 8 - Features; System ACE CF and CompactFlash Connector
8 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board Features The SP605 board provides the following features: • 1. Spartan-6 XC6SLX45T-3FGG484 FPGA • 2. 128 MB DDR3 Component Memory • 3. SPI x4 Flash • 4. Linear BPI Flash • 5. System ACE CF an...
Page 9 - Power On/Off slide switch; Block Diagram; shows a high-level block diagram of the SP605 and its peripherals.; SP605 Features and Banking
SP605 Hardware User Guide www.xilinx.com 9 UG526 (v1.1.1) February 1, 2010 Overview • 17. Switches ♦ Power On/Off slide switch ♦ System ACE CF Reset pushbutton ♦ System ACE CF bitstream image select DIP switch ♦ Mode DIP switch • 18. VITA 57.1 FMC LPC Connector • Configuration Options ♦ 3. SPI x4 Fl...
Page 10 - Related Xilinx Documents
10 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board Related Xilinx Documents Prior to using the SP605 Evaluation Board, users should be familiar with Xilinx resources. See the following locations for additional documentation on Xilinx tools a...
Page 11 - Detailed Description
SP605 Hardware User Guide www.xilinx.com 11 UG526 (v1.1.1) February 1, 2010 Detailed Description 4 Linear BPI Flash x16 Numonyx JS28F256P30T95 19 5 SystemACE CompactFlash Socket XCCACE-TQ144I Controller 20 6 USB JTAG Conn. (USB Mini-B) USB JTAG Download Circuit 32 7 Clock Generation 200 MHz OSC, osc...
Page 12 - Configuration; “Configuration Options.”; References; Spartan-6 FPGA Configuration User Guide
12 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board 1. Spartan-6 XC6SLX45T- 3 FGG4 8 4 FPGA A Xilinx Spartan-6 XC6SLX45T-3FGG484 FPGA is installed on the Embedded Development Board. References See the Spartan-6 FPGA Data Sheet. [Ref 1] Config...
Page 13 - MB DDR; and; I/O Voltage Rail of FPGA Banks; FPGA Bank; Termination Resistor Requirements; Signal Name
SP605 Hardware User Guide www.xilinx.com 13 UG526 (v1.1.1) February 1, 2010 Detailed Description I/O Voltage Rails There are four available banks on the XC6SLX45T-3FGG484 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.5V DDR3 component memory interface of Spartan-6 FP...
Page 14 - DDR3 Component Memory Connections
14 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board Table 1-5 shows the connections and pin numbers for the DDR3 Component Memory. Table 1-4: FPGA On-Chip (OCT) Termination External Resistor Requirements U1 FPGA Pin FPGA Pin Number Board Conn...
Page 15 - DDR3 SDRAM Specification
SP605 Hardware User Guide www.xilinx.com 15 UG526 (v1.1.1) February 1, 2010 Detailed Description References See the Micron Technology, Inc. DDR3 SDRAM Specification for more information. [Ref 12] Also, see the Spartan-6 FPGA Memory Controller User Guide . [Ref 3] T1 MEM1_DQ9 C3 DQ9 U3 MEM1_DQ10 A2 D...
Page 16 - J17 SPI Flash Programming Header; ilk
16 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board 3 . SPI x4 Flash The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are...
Page 17 - See the Winbond; SPI x4 Memory Connections
SP605 Hardware User Guide www.xilinx.com 17 UG526 (v1.1.1) February 1, 2010 Detailed Description References See the Winbond Serial Flash Memory Data Sheet for more information. [Ref 13] See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4] Table 1-6: SPI x4 Memory Connecti...
Page 18 - For details on configuring the FPGA, see; Linear BPI Flash Interface; U1 FPGA Pin
18 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board 4. Linear BPI Flash A Numonyx JS28F256P30 Linear Flash memory (U25) on the SP605 ( Figure 1-5 ) provides 32 MB of non-volatile storage that can be used for configuration as well as software ...
Page 19 - Linear Flash Connections
SP605 Hardware User Guide www.xilinx.com 19 UG526 (v1.1.1) February 1, 2010 Detailed Description E22 FLASH_A16 55 A17 E20 FLASH_A17 18 A18 F22 FLASH_A18 17 A19 F21 FLASH_A19 16 A20 H19 FLASH_A20 11 A21 H18 FLASH_A21 10 A22 F20 FLASH_A22 9 A23 G19 FLASH_A23 26 A24 AA20 FPGA_D0_DIN_MISO_MISO1 34 DQ0 R...
Page 20 - FPGA Design Considerations for the Configuration Flash; StrataFlash Embedded Memory Data Sheet
20 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board FPGA Design Considerations for the Configuration Flash The SP605 has the P30 BPI flash connected to the FPGA dual use configuration pins and is not shared. It can be used to configure the FP...
Page 21 - A solid green status LED indicates a successful download; The System ACE CF MPU port (; System ACE CF Connections
SP605 Hardware User Guide www.xilinx.com 21 UG526 (v1.1.1) February 1, 2010 Detailed Description System ACE CF error and status LEDs indicate the operational state of the System ACE CF controller: • A blinking red error LED indicates that no CompactFlash card is present • A solid red error LED indic...
Page 22 - See the System ACE CF product page for more information at; JTAG Chain Diagram
22 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board References See the System ACE CF product page for more information at http://www.xilinx.com/support/documentation/system_ace_solutions.htm . In addition, see the System ACE CompactFlash Solu...
Page 23 - . When the VITA 57.1 FMC LPC expansion connector is populated; See the Epson
SP605 Hardware User Guide www.xilinx.com 23 UG526 (v1.1.1) February 1, 2010 Detailed Description FMC bypass jumper J19 must be connected between pins 1-2 (bypass) to enable JTAG access to the FPGA on the basic SP605 board (without FMC expansion modules installed), as shown in Figure 1-7 . When the V...
Page 25 - The SP605 provides access to 4 MGTs.; SP605 Clock Source Connections
SP605 Hardware User Guide www.xilinx.com 25 UG526 (v1.1.1) February 1, 2010 Detailed Description SMA Connectors (Differential) A high-precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50-ohm SMA connectors J38 (N) and J41 (P). 8 . Multi-Gigabit T...
Page 26 - MA MGT Connector
26 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board X-Ref Target - Figure 1-10 Figure 1-10: GTP SMA Clock GND1GND2GND3GND4GND5GND6GND7 S IG GND1GND2GND3GND4GND5GND6GND7 S IG GND1GND2GND3GND4GND5GND6GND7 S IG GND1GND2GND3GND4GND5GND6GND7 S IG ...
Page 28 - PCI Express Endpoint Connectivity; PCIe Edge Connector Connections
28 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board 9. PCI Express Endpoint Connectivity The 1-lane PCIe edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1 application. The Spartan-6 FPGA GTP MGT is used for the multi-g...
Page 29 - See the
SP605 Hardware User Guide www.xilinx.com 29 UG526 (v1.1.1) February 1, 2010 Detailed Description References See the Spartan-6 FPGA GTP Transceivers User Guide for more information. [Ref 6] Also, see the following websites for more information about the Spartan-6 FPGA Integrated Endpoint Block for PC...
Page 30 - SFP Module Connector; . The SFP module connections are shown; SFP Module Control and Status; Test Point J15; SFP Module Connections
30 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board 10. SFP Module Connector The board contains a small form-factor pluggable (SFP) connector and cage assembly that accepts SFP modules. The SFP interface is connected to MGT Bank 123 on the FP...
Page 31 - The; PHY Configuration Pins; Ethernet PHY Connections
SP605 Hardware User Guide www.xilinx.com 31 UG526 (v1.1.1) February 1, 2010 Detailed Description 11. 10/100/1000 Tri-Speed Ethernet PHY The SP605 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports a GMII interface from the FP...
Page 32 - See the Marvell
32 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board References See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information. [Ref 17] Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide . [Ref 7] U22 PHY_RXD7...
Page 33 - Getting Started Guide; Refer to the; USB Type B Pin Assignments and Signal Definitions
SP605 Hardware User Guide www.xilinx.com 33 UG526 (v1.1.1) February 1, 2010 Detailed Description 12. USB-to-UART Bridge The SP605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation ...
Page 34 - ) supports the IIC protocol to allow the board to read the; DVI Controller Connections
34 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board 1 3 . DVI CODEC A DVI connector (P3) is present on the board to support an external video monitor. The DVI circuitry utilizes a Chrontel CH7301C (U31) capable of 1600 X 1200 resolution with ...
Page 36 - , and U4 is not write protected; IIC Bus Connections; IIC Addre
36 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board 8 -Kb NV Memory The SP605 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U4). The IIC address of U4 is 0b1010100 , and U4 is not write protected (WP pin ...
Page 37 - See the ST Micro; IIC Memory Connections
SP605 Hardware User Guide www.xilinx.com 37 UG526 (v1.1.1) February 1, 2010 Detailed Description References See the ST Micro M24C08 Data Sheet for more information. [Ref 18] In addition, see the Xilinx XPS IIC Bus Interface Data Sheet . [Ref 8] Table 1-20: IIC Memory Connections U1 FPGA Pin Schemati...
Page 38 - defines the status LEDs.; Status LEDs
38 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board 15. Status LEDs Table 1-21 defines the status LEDs. Table 1-21: Status LEDs Reference Designator Signal Name Color Label Description DS1 FMC_PWR_GOOD_FLASH_RST_B Green FMC PWR GD FMC Power G...
Page 39 - Ethernet PHY Status LEDs
SP605 Hardware User Guide www.xilinx.com 39 UG526 (v1.1.1) February 1, 2010 Detailed Description Ethernet PHY Status LEDs The Ethernet PHY status LEDs (DS11-DS13) are mounted in right-angle plastic housings to make them visible on the connector end of the board when the SP605 board is installed into...
Page 40 - FPGA INIT and DONE LEDs
40 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and configuration status LEDs are present on the SP605. The red INIT LED DS17 comes on momentarily after the FPGA powers up and durin...
Page 41 - User LEDs; The SP605 provides four active-High green LEDs as described in; User LEDs; GPIO LED 3
SP605 Hardware User Guide www.xilinx.com 41 UG526 (v1.1.1) February 1, 2010 Detailed Description 16. User I/O The SP605 provides the following user and general purpose I/O capabilities: • User LEDs • User Pushbutton Switches • User DIP Switch • User SIP Header • User SMA GPIO User LEDs The SP605 pro...
Page 42 - User Pushbutton Switches; Pushbutton Switch Connections
42 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board User Pushbutton Switches The SP605 provides five active-High pushbutton switches: SW4, SW5, SW6, SW7 and SW8. The five pushbuttons all have the same topology as the sample shown in Figure 1-...
Page 43 - User DIP Switch; User DIP Switch S2
SP605 Hardware User Guide www.xilinx.com 43 UG526 (v1.1.1) February 1, 2010 Detailed Description User DIP Switch The SP605 includes an active-High four-pole DIP switch, as described in Figure 1-17 and Table 1-25 . Three poles (switches 1-3) are pulled up to 2.5V, and one pole (switch 4) is pulled up...
Page 44 - User SIP Header; User SIP Header J55; User SIP Header Connections
44 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board User SIP Header The SP605 includes a 6-pin single-inline (SIP) male pin header (J55) for FPGA GPIO access. Four pins of J55 are wired to the FPGA through 200 ohm series resistors and a level...
Page 45 - User SMA GPIO
SP605 Hardware User Guide www.xilinx.com 45 UG526 (v1.1.1) February 1, 2010 Detailed Description User SMA GPIO The SP605 includes an pair of SMA connectors for GPIO as described in Figure 1-19 and Table 1-27 . X-Ref Target - Figure 1-19 Figure 1-19: User SMA GPIO Table 1-27: User SMA Connections U1 ...
Page 46 - The SP605 Evaluation board includes the following switches:; “Power Management,” page 52; Power On/Off Slide Switch SW2; CAUTION; au; PCIe
46 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board 17. Switches The SP605 Evaluation board includes the following switches: • Power On/Off Slide Switch SW2 • FPGA_PROG_B Pushbutton SW3 (Active-Low) • SYSACE_RESET_B Pushbutton SW9 (Active-Low...
Page 47 - CF and CompactFlash Connector,” page 20; FPGA PROG_B Pushbutton SW3; System ACE CF RESET_B Pushbutton SW9
SP605 Hardware User Guide www.xilinx.com 47 UG526 (v1.1.1) February 1, 2010 Detailed Description FPGA_PROG_B Pushbutton SW 3 (Active-Low) The SW3 switch ( Figure 1-21 ) grounds the FPGA PROG_B pin when pressed. This action clears the FPGA. See the Spartan-6 FPGA data sheet for more information on cl...
Page 48 - “5. System ACE CF and CompactFlash; System ACE CF CompactFlash Image Select DIP Switch S1
48 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High) System ACE CF CompactFlash (CF) image select DIP switch S1, switches 1–3 ( Figure 1-23 ) select which CF resident bitstrea...
Page 49 - DIP switch SW1 sets the FPGA mode as shown in; For more information, refer to the; FPGA Mode DIP Switch SW1
SP605 Hardware User Guide www.xilinx.com 49 UG526 (v1.1.1) February 1, 2010 Detailed Description Mode DIP Switch SW1 (Active-High) DIP switch SW1 sets the FPGA mode as shown in Figure 1-24 and Table 1-30, page 55 . References For more information, refer to the Spartan-6 FPGA Configuration User Guide...
Page 51 - shows the VITA 57.1 FMC LPC connections. The connector pinout is in; VITA 57.1 FMC LPC Connections
SP605 Hardware User Guide www.xilinx.com 51 UG526 (v1.1.1) February 1, 2010 Detailed Description Table 1-28 shows the VITA 57.1 FMC LPC connections. The connector pinout is in Appendix B, “VITA 57.1 FMC LPC Connector Pinout.” Table 1-28: VITA 57.1 FMC LPC Connections J63 FMC LPC Pin Schematic Net Na...
Page 52 - AC Adapter and 12V Input Power Jack/Switch
52 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board Power Management AC Adapter and 12V Input Power Jack/Switch The SP605 is powered from a 12V source that is connected through a 6-pin (2X3) right angle Mini-Fit type connector J18. The AC-to-...
Page 53 - Onboard Power Regulation; Onboard Power Regulators; Power
SP605 Hardware User Guide www.xilinx.com 53 UG526 (v1.1.1) February 1, 2010 Power Management Onboard Power Regulation Figure 1-25 shows the SP605 onboard power supply architecture. The SP605 uses Texas Instruments power controllers for primary core power control and monitoring. X-Ref Target - Figure...
Page 54 - Onboard Power System Devices
54 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board Voltage and current monitoring and control are available for selected power rails through Texas Instruments' Fusion Digital Power™ graphical user interface (GUI). Both onboard TI power contr...
Page 55 - Configuration Options; “5. System ACE CF and CompactFlash Connector,” page 20; SP605 FPGA Configuration Modes
SP605 Hardware User Guide www.xilinx.com 55 UG526 (v1.1.1) February 1, 2010 Configuration Options Configuration Options The FPGA on the SP605 Evaluation Board can be configured by the following methods: • “3. SPI x4 Flash,” page 16 • “4. Linear BPI Flash,” page 18 • “5. System ACE CF and CompactFlas...
Page 57 - Appendix A; Default Jumper and Switch Settings; shows the default switch settings and; Default Switch Settings; REFDES
SP605 Hardware User Guide www.xilinx.com 57 UG526 (v1.1.1) February 1, 2010 Appendix A Default Jumper and Switch Settings Table A-1 shows the default switch settings and Table A-2, page 58 shows the default jumper settings for the SP605. Table A-1: Default Switch Settings REFDES Function/Type Defaul...
Page 58 - Jumper
58 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Appendix A: Default Jumper and Switch Settings Table A-2: Default Jumper Settings Jumper REFDES Function Default FMC JTAG Bypass J19 exclude FMC LPC connector J2 Jump 1-2 SFP Module J22 SFP Full BW Jump 1-2 J44 SFP Enabled J...
Page 59 - Appendix B; VITA 57.1 FMC LPC Connector Pinout; shows the pinout of the FMC LPC connector. Pins marked NC are not; FMC LPC Connector Pinout
SP605 Hardware User Guide www.xilinx.com 59 UG526 (v1.1.1) February 1, 2010 Appendix B VITA 57.1 FMC LPC Connector Pinout Figure B-1 shows the pinout of the FMC LPC connector. Pins marked NC are not connected. X-Ref Target - Figure B-1 Figure B-1: FMC LPC Connector Pinout K J H G F E D C B A 1 NC NC...
Page 61 - Appendix C; Constraints Guide
SP605 Hardware User Guide www.xilinx.com 61 UG526 (v1.1.1) February 1, 2010 Appendix C SP605 Master UCF The UCF template is provided for designs that target the SP605. Net names provided in the constraints below correlate with net names on the SP605 rev. C schematic. On identifying the appropriate p...
Page 67 - Appendix D; For additional information, see; Additional documentation:; Numonyx
SP605 Hardware User Guide www.xilinx.com 67 UG526 (v1.1.1) February 1, 2010 Appendix D References This appendix provides references to documentation supporting Spartan-6 FPGAs, tools, and IP. For additional information, see www.xilinx.com/support/documentation/index.htm . Xilinx documents supporting...
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