Xilinx UG181 - Manual - manualsarea.com

Page 2 - Date

SPI-4.2 Lite v4.3 User Guide www.xilinx.com UG181 June 27, 2008 Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copie...

Page 3 - Table of Contents; Preface: About This Guide

SPI-4.2 Lite v4.3 User Guide www.xilinx.com UG181 June 27, 2008 Table of Contents Preface: About This Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Conventions . . . . . . . . . . . . . . . . ...

Page 7 - Schedule of Figures; Chapter 2: Core Architecture

Schedule of Figures Chapter 2: Core Architecture Figure 2-1: SPI-4.2 Lite Core in a Typical Link Layer Application . . . . . . . . . . . . . . . . . . . 18 Figure 2-2: Sink Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 2-3: Sourc...

Page 8 - Chapter 6: Special Design Considerations

www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Figure 4-30: Addressable Status FIFO Interface: 4-Channel Configuration . . . . . . . . . . . 89 Figure 4-31: Addressable Status FIFO Interface: 256-channel configuration . . . . . . . . . . 90 Figure 4-32: Addressable Status FIFO Inter...

Page 9 - Schedule of Tables

SPI-4.2 Lite v4.3 User Guide www.xilinx.com UG181 June 27, 2008 Chapter 2: Core Architecture Table 2-1: Sink SPI-4.2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 2-2: Sink Control and Status Signals . . . . . . . . . . . . . . . . . . ....

Page 11 - Preface; About This Guide; Contents

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 11 UG181 June 27, 2008 R Preface About This Guide This user guide describes the function and operation of the Xilinx LogiCORE™ IP SPI-4.2 (PL4) Lite core, and provides information about designing, customizing, and implementing the core. Contents This guide...

Page 12 - Conventions; Typographical

12 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Preface: About This Guide R Conventions This document uses the following conventions. An example illustrates each convention. Typographical The following typographical conventions are used in this document: Convention Meaning or Use ...

Page 13 - Online Document; Convention

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 13 UG181 June 27, 2008 Conventions R Online Document The following conventions are used in this document: Convention Meaning or Use Example Blue text Cross-reference link to a location in the current document See the section “Additional Resources” for deta...

Page 15 - Chapter 1; Introduction; About the Core; Recommended Design Experience

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 15 UG181 June 27, 2008 R Chapter 1 Introduction The SPI-4.2 (PL4) Lite core implements and is functionally compliant to the OIF-SPI-4-02.1 System Packet Interface Phase 2 specification and supports both VHDL and Verilog design environments. This chapter in...

Page 16 - Technical Support; Feedback; Document

16 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 1: Introduction R Technical Support To obtain technical support specific to the SPI-4.2 Lite core, visit www.xilinx.com/support . Questions are routed to a team of engineers with expertise using the SPI-4.2 Lite core. Xilinx ...

Page 17 - Chapter 2; Core Architecture; System Overview; Source Core

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 17 UG181 June 27, 2008 R Chapter 2 Core Architecture This chapter describes the SPI-4.2 Lite core architecture and interface signals. System Overview The SPI-4.2 Lite core is comprised of two separate cores that enable the transmission (Source core) and re...

Page 18 - Sink Core; SPI-4.2 Lite Core in a Typical Link Layer Application

18 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 2: Core Architecture R data access and facilitates integration within a system. Dedicated signals are used to configure the Sink and Source cores in circuit and monitor a suite of status registers. Sink Core The Sink core rec...

Page 19 - Sink Core Interfaces

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 19 UG181 June 27, 2008 Sink Core Interfaces R standard FIFO interface, and the FIFO read and write operations are performed in independent clock domains. The Source core implements the following features: • Supports 32-bit or 64-bit user data width. • Opti...

Page 20 - Sink Core Block Diagram

20 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 2: Core Architecture R The functional modules and signals which comprise the different interfaces are shown in Figure 2-2 and defined in tables in the following sections. Figure 2-2: Sink Core Block Diagram SPI-4.2 Lite Sink ...

Page 22 - Sink User Interface; Control and Status Interface; Sink Control and Status Interface

22 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 2: Core Architecture R Sink User Interface The Sink User Interface includes all signals other than those on the SPI-4.2 Interface. The high-performance logic on the Sink back-end enables the user interface to run at higher fr...

Page 23 - Sink FIFO Interface

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 23 UG181 June 27, 2008 Sink Core Interfaces R Sink FIFO Interface The Sink FIFO Interface signals allow you to access the data (received on the SPI-4.2 Interface) that is stored in the FIFO. The signals on this interface is defined in Table 2-3 . SnkOof Ou...

Page 26 - Sink Static Configuration Interface

26 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 2: Core Architecture R Sink Static Configuration Interface These signals are inputs to the core that are statically driven by setting them to a constant value in the top-level wrapper file. The SPI-4.2 Lite release includes a...

Page 29 - Sink Clocking Interface

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 29 UG181 June 27, 2008 Sink Core Interfaces R Sink Clocking Interface The Sink core supports two clocking implementations: embedded clocking and user clocking. The embedded clocking configuration provides a complete solution with the clock circuitry embedd...

Page 30 - Source Core Interfaces; Sink Core Clocks: User Clocking

30 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 2: Core Architecture R Source Core Interfaces The Source core includes five functional modules: • Source Data FIFO • Source Data Transmit • Source Status Registers • Source Calendar • Source Status Receive The Source core is ...

Page 31 - Source Core Block Diagram and I/O Interface Signals

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 31 UG181 June 27, 2008 Source Core Interfaces R Figure 2-3 illustrates the functional modules and signals in each interface—all signals are defined in sections following this illustration. Source SPI-4.2 Interface The SPI-4.2 interface uses LVDS I/O buffer...

Page 32 - Source User Interface

32 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 2: Core Architecture R In addition to transmitting 16-bit data words, the SPI-4.2 interface also receives flow control data at 1/4 rate of its data interface. The 2-bit status received can be presented to you in 2 interfaces:...

Page 33 - Source Control and Status Interface

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 33 UG181 June 27, 2008 Source Core Interfaces R Source Control and Status Interface The Source Control and Status signals either control the operation of the entire Source core or provide status information that is not associated with a particular channel ...

Page 35 - Source FIFO Interface

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 35 UG181 June 27, 2008 Source Core Interfaces R Source FIFO Interface The Source FIFO Interface signals allow you to write data into the FIFO to be transmitted on the SPI-4.2 Interface. Table 2-12 defines the Source FIFO signals. Table 2-12: S ource FIFO S...

Page 37 - Source Static Configuration Interface

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 37 UG181 June 27, 2008 Source Core Interfaces R Source Static Configuration Interface These signals are inputs to the core that are statically driven by setting them to a constant value in the top-level wrapper file. The SPI-4.2 Lite release includes a wra...

Page 39 - Source Clocking Interface

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 39 UG181 June 27, 2008 Source Core Interfaces R Source Clocking Interface The Source core supports two clocking implementations: master clocking and slave clocking. The master clocking configuration provides a complete solution with the clock circuitry emb...

Page 43 - Chapter 3; Generating the Core; CORE Generator Graphical User Interface; Main window

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 43 UG181 June 27, 2008 R Chapter 3 Generating the Core The SPI-4.2 Lite core is a fully configurable implementation of the OIF-SPI4-02.1 Specification . Using the CORE Generator GUI, you can configure the core and customize the delivered files including th...

Page 44 - Main Screen; Component Name; Number of Channels; Sink Status Options Screen; SPI-4.2 Lite Sink and Source Main Customization Screen

44 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 3: Generating the Core R Main Screen The main SPI-4.2 Lite screen defines the component name, core options, and UCF File options. Component Name The Component Name is the base name of the output files generated for the core. ...

Page 45 - Calendar; Flow Control; Status Interface

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 45 UG181 June 27, 2008 Sink Status Options Screen R Calendar Options in this section affect the behavior of the Sink core with respect to its calendar and status interfaces. Iterations of Calendar Sequence Before DIP2 This is the value of static configurat...

Page 46 - Sink Other Options Screen; Synchronization

46 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 3: Generating the Core R Rate This is the value of static configuration signal RSClkDiv ; it selects the frequency of RSClk with respect to RDClk. Alignment This is the value of static configuration signal RSClkPhase ; it det...

Page 47 - Clocking; Embedded Clocking; Source Status Options Screen

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 47 UG181 June 27, 2008 Source Status Options Screen R to normal. The valid range is the Almost Full Assert value to 508 and is also measured from the full level. Clocking Clock Mode The Sink core netlist will contain a complete clocking solution if Embedde...

Page 48 - Status FIFO Interface; Number of DIP2 Matches; Source Other Options Screen; Bursting; Number of Data Cycles Before Training

48 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 3: Generating the Core R Status Interface Status FIFO Interface This option selects whether the Source core netlist is generated with an addressable or transparent user status interface. For more information, see the “Source ...

Page 49 - Complete Bursts Only; Segmentation of Bursts at; FIFO Threshold; Master Clocking

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 49 UG181 June 27, 2008 Source Other Options Screen R Burst Size in Credits This is the value of static configuration signal SrcBurstLen; it is the maximum burst length in credits. The valid range is from 1 to 63. Burst Mode This is the value of static conf...

Page 50 - Calendar COE File Format

50 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 3: Generating the Core R Calendar COE File Format The initial contents of the calendar can be assigned by specifying the desired information in a separate text file called a COE file. To select and load a COE file, first crea...

Page 51 - Chapter 4; Designing with the Core; General Design Guidelines; Know the Degree of Difficulty; Understand Signal Pipelining

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 51 UG181 June 27, 2008 R Chapter 4 Designing with the Core This chapter contains general design guidelines, detailed descriptions about the behavior of each interface, example waveforms, and implementation considerations. To design an application using the...

Page 52 - Keep it Registered; Make Only Allowed Modifications; Reset core; Deassert core reset

52 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Keep it Registered The best method to simplify timing and increase system performance in an FPGA design is to keep everything registered. That is, all inputs and outputs from the user application ...

Page 53 - Programming calendar after reset; Basic Operation; Sink Data Path: Example 1

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 53 UG181 June 27, 2008 Sink Core R • Initializing Status Calendar After the core exits the reset mode, the sink and status calendars must be initialized or programmed. There are two ways to do this: ♦ Initialize calendar with a default value : Using the CO...

Page 54 - Sink Data Path: Example 2; Received SOPs that are less than eight cycles apart

54 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R channel 2 and an SOP for channel 1, followed by three 16-bit words. The last control word (C4) is an EOP for channel 1. The data received on the SPI-4.2 Interface is processed and stored in the Si...

Page 58 - Control and Status Signals; Sink Control and Status Signals; Sink Bus Error Status; Control Word

58 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Sink User Interface The Sink User Interface includes all the signals to the core other than those on the SPI-4.2 Interface (See “SPI-4.2 Interface,” page 53 ). The high performance Sink back-end e...

Page 59 - Sink Bus Error; Sink FIFO Interface Signals; Sink FIFO Almost Empty; Sink Training Valid Status

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 59 UG181 June 27, 2008 Sink Core R ♦ SnkBusErrStat[5]: Control word with payload bit not set and non-zero address (excluding Training Control word). ♦ SnkBusErrStat[7:6] : Tied to zero. (reserved) If the core receives two (or more) back-to-back payload con...

Page 60 - Sink FIFO Empty

60 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R deasserted on the next clock cycle. The Sink FIFO read logic should then evaluate the SnkFFEmpty_n signal to verify that there is no data in the FIFO in case an additional word was simultaneously ...

Page 61 - Sink Overflow; Sink Status and Flow Control Signals

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 61 UG181 June 27, 2008 Sink Core R operations occurring on the sink user interface. Configure the SnkAFThresAssert value according to your specific system requirements. See “FifoAFMode and Sink Almost Full,” page 67 for a description of the behavior of Sin...

Page 62 - Sink Calendar Initialization; Initializing the Calendar In-Circuit; Status FIFO Calendar and Status Memory Block Diagram

62 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Sink Calendar Initialization There are two ways to initialize the Sink Calendar: by loading a COE file in the CORE Generator GUI or initializing in-circuit at startup. Using the Generator GUI load...

Page 63 - Sink Flow Control; Automatic; Manual

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 63 UG181 June 27, 2008 Sink Core R SnkCalAddr=1 , and so forth, until the end of the Calendar is reached, as defined by SnkCalendar_Len . The waveform in Figure 4-7 illustrates the programming of the Sink Calendar. In this example, SnkCalendar_Len is set t...

Page 64 - Typical Flow Control Implementation for 4-Channel System

64 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Status for 16 channels each clock cycle can be written. The SnkStatAddr bus is used to select which 16 channels are written, and the core supports configurations of 1–256 channels. The 16 channels...

Page 65 - shows the status written into; Sink Status FIFO Interface: Example 2

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 65 UG181 June 27, 2008 Sink Core R Sink Status FIFO Interface: Example 1 This example illustrates writing to the Status FIFO Interface for a 10-channel SPI-4.2 Lite Sink core as shown in Figure 4-9 . Because there are fewer than 17 channels, the Sink Statu...

Page 66 - Sink Status FIFO Status Interface: Example 3

66 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Sink Status FIFO Status Interface: Example 3 This example illustrates status received on the user interface and written to the SPI-4.2 bus. Figure 4-11 shows a RStat waveform for a calendar length...

Page 67 - Insertion of DIP2 Errors; Sink Static Configuration Signals; FifoAFMode and Sink Almost Full; FIFO Almost Full Mode “00”

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 67 UG181 June 27, 2008 Sink Core R Insertion of DIP2 Errors The sink core enables you to force the insertion of DIP2 errors for use during system testing and debugging. This is supported by the SnkDIP2ErrRequest signal. When the SnkDIP2ErrRequest signal is...

Page 68 - FIFO Almost Full Mode “01”

68 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R FIFO Almost Full Mode “01” When the FIFO Almost Full Mode ( FifoAFMode ) is set to “01,” and the Sink core becomes Almost Full, the Sink interface remains in-frame ( SnkOof deasserted), and the Si...

Page 69 - Sink Data Capture Implementation; Static Alignment; DCM Alignment Implementation Considerations; FIFO Almost Full Mode “10” or “11”

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 69 UG181 June 27, 2008 Sink Core R FIFO Almost Full Mode “10” or “11” When the FIFO Almost Full Mode ( FifoAFMode ) is set to “10” or “11,” and the Sink core becomes Almost Full, the Sink Status logic will continue to drive out user status information (tha...

Page 70 - Synchronization and Start-up

70 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R setting has the added advantage of providing a benchmark of the system margin, based on the UI (unit interval or bit time). System Margin (ps) = UI(ps) * (working phase shift range/128) Xilinx doe...

Page 71 - Hunt; Sync Wait; Sink Startup Sequence State Machine

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 71 UG181 June 27, 2008 Sink Core R Figure 4-15 shows a state machine diagram illustrating the Sink core startup sequence and error condition processing. Reset The Sink core remains in the Reset state until the following conditions are true: • Reset_n is de...

Page 72 - Sync Data; Error Handling

72 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Sync Data In the Sync Data state, normal core operation is enabled. In this state, the Sink core continuously checks DIP-4 parity, stores data received on RDat[15:0] into the Sink FIFO, and sends ...

Page 73 - Sink FIFO Burst Error; Short Packet Support

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 73 UG181 June 27, 2008 Sink Core R Figure 4-16 illustrates back-to-back short packets. In this example there are four channels that are each sending 17-byte packets with a maximum burst of 16 bytes. Sink FIFO Burst Error When data received on RDat is termi...

Page 74 - Sequential Payload Control Words; Sink DIP-4 Error Handling; Sequential Payload Control Word Example

74 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R • SnkBusErrStat[5]: Control word with payload bit not set and non-zero address (excluding Training Control word) • SnkBusErrStat[7:6]: Unused and tied to zero (reserved) If the core receives two (...

Page 76 - Reserved Control Words; Example of Error Flag SnkFFPayloadErr

76 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Reserved Control Words As defined by the OIF SPI-4.2 specification, a reserved control word contains an SOP, but the payload control bit ( RDat[15] ) is not set to a one. If this occurs and is fol...

Page 77 - Source Data Path: Example 1

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 77 UG181 June 27, 2008 Source Core R Source Data Path: Example 1 An example of the data received on the user interface and subsequently transmitted on the SPI-4.2 Interface is shown in Figure 4-21 . In this illustration, a 14-byte packet of data is written...

Page 81 - Transmitting Training Patterns

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 81 UG181 June 27, 2008 Source Core R Transmitting Training Patterns Training patterns are transmitted at startup (after reset) until the core acquires synchronization on the FIFO Status Channel. Subsequently, if the parameter DataMaxT or AlphaData are not ...

Page 82 - Transmitting Idle Cycles; Source Control and Status Signals; SrcFFMod

82 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Transmitting Idle Cycles Idle cycles are sent on the SPI-4.2 Interface only when there is no data in the FIFO. The core will also insert idle cycles when the control signal IdleRequest (see Table ...

Page 83 - Source FIFO Interface Signals; Source FIFO Almost Full

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 83 UG181 June 27, 2008 Source Core R The control signal TrainingRequest is used to request that training patterns be sent out of the Source SPI-4.2 interface. When this signal is asserted, data transmission is halted on the next burst boundary and training...

Page 84 - Source FIFO Overflow; Source FIFO Almost-full Condition

84 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Source FIFO Overflow Figure 4-25 shows the overflow response of the Source FIFO. The assertion of SrcFFAlmostFull_n indicates that the FIFO is almost full, and that data should no longer be writte...

Page 85 - Source Status and Flow Control Signals; Writing to the Source FIFO

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 85 UG181 June 27, 2008 Source Core R Writing to the Source FIFO A pause to a transfer on a credit (16 bytes) boundary is illustrated in Figure 4-26 . In the example shown, two packets for unique channels are transferred into the FIFO. You write 32 bytes of...

Page 86 - Transparent Status Interface; Source Calendar Initialization; Typical User Design Example

86 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R To enable designing back-end user logic, the Source core presents status information in two ways: • Addressable Status Interface . This interface allows polling the status of 16 channels at a time...

Page 87 - Source Flow Control: Addressable Status Interface

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 87 UG181 June 27, 2008 Source Core R Initializing the Calendar In-Circuit At start-up, you can program the Source calendar buffer by first deasserting Source Enable ( SrcEn ), then using the calendar write enable, address bus, and data bus. SrcCalAddr is u...

Page 88 - Addressable Status FIFO Interface: Example 1; Addressable Status FIFO Interface

88 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R • ... • Bank 14: SrcStatAddr[3:0]=14 for channels 239 to 224 • Bank 15: SrcStatAddr[3:0]=15 for channels 255 to 240 The status that is accessed is mapped to the 16-bit bus as follows (assuming Src...

Page 89 - Addressable Status FIFO Interface: Example 2

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 89 UG181 June 27, 2008 Source Core R The Source Status Channel ( SrcStatCh[7:0] ) indicates which channel status was last updated on the SPI-4.2 Interface and is qualified by the Source Status Channel Valid signal ( SrcStatChValid=1 ). SrcStatChValid enabl...

Page 90 - Addressable Status FIFO Interface: Example 3

90 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R • Bank 1: SrcStatAddr[3:0]= 0001, for channels 31 to 16 • Bank 2: SrcStatAddr[3:0]= 0010, for channels 47 to 32 • Bank 3: SrcStatAddr[3:0]= 0011, for channels 63 to 48 • ... • Bank 15: SrcStatAddr...

Page 91 - Source Flow Control: Transparent Status Interface

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 91 UG181 June 27, 2008 Source Core R internal status path clock ( SrcStatClk ) is synchronous to the external status path clock ( TSClk ). In other words, SrcStatClk is tied to TSClk_GP . This enables one to always be accessing the last updated status info...

Page 93 - Source Static Configuration Signals; Source Burst Mode

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 93 UG181 June 27, 2008 Source Core R Source Static Configuration Signals The source static configuration signals are inputs to the core, statically driven to determine the behavior of the core. See Table 2-15, page 38 for a full list of static configuratio...

Page 94 - Source Burst Mode Example; Example Of Source Burst Mode = 0

94 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Source Burst Mode Example SrcBurstLen equals 2 credits and 1.5 credits are written into the FIFO followed by 0.5 credits. Figure 4-35 illustrates the behavior of the Source core when SrcBurstMode=...

Page 95 - RESET; SYNC; Source Startup Sequence State Machine

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 95 UG181 June 27, 2008 Source Core R RESET The Source core remains in the RESET state until the Reset_n signal is deasserted. When in the RESET state, the Source core transmits idle patterns on TDat[15:0] and the Status FIFO is driven to be satisfied (“10”...

Page 96 - Source Behavior Before Synchronization

96 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 4: Designing with the Core R Error Handling This section describes how the Source core handles the receipt of non-compliant SPI-4.2 data and subsequent error handling in a number of common scenarios. This section also provide...

Page 97 - Source DIP-2 Error Handling

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 97 UG181 June 27, 2008 Source Core R ♦ Action: The Source core will transmit idle cycles when Reset_n is asserted. When Reset_n is deasserted, the core will initiate the synchronization start-up sequence. • Case 2: If the core receives a number of consecut...

Page 99 - Chapter 5; Constraining the Core; Overview; Sink Core Required Constraints; Timing Constraints

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 99 UG181 June 27, 2008 R Chapter 5 Constraining the Core This chapter describes the timing and placement constraints required by the SPI-4.2 Lite core to meet the performance requirements, including a set of optional constraints. These constraints are prov...

Page 100 - Time Names for Clocks; Timespecs for Clocks

100 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 5: Constraining the Core R the following examples, the target performance is 340 Mbps. Please ensure that modifications to these constraints do not create paths that are unconstrained. Time Names for Clocks The following Sin...

Page 101 - DCM and Static Alignment Constraints; Phase Shift for DCM

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 101 UG181 June 27, 2008 Sink Core Required Constraints R • NET "<snk_instance_name>/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/rs clk_rst" MAXDELAY = 5.8 ns; • NET "<snk_instance_name>/U0/pl4_lite_snk_reset01/snk_stat_clk_gen/ reset_ou...

Page 102 - Placement Constraints

102 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 5: Constraining the Core R • INST "<snk_instance_name>/U0/clk0/rdclk_dcm0" IOBDELAY_VALUE = 0; Placement Constraints Although the SPI-4.2 Lite core does not require fixed pinouts, there are several placement co...

Page 103 - IOB Register Packing; Sink Core Optional Constraints; IDelayCtrl

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 103 UG181 June 27, 2008 Sink Core Optional Constraints R • INST "RDClk*" LOC = "Bank3"; IOB Register Packing The following constraints are mandatory for the Sink core. It ensures that the output register 3 of the RStat and RSClk signals are...

Page 104 - Area Group Constraints; Source Core Required Constraints; Timenames for Clocks

104 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 5: Constraining the Core R • INST "<sink_instance_name>/U0/pl4_lite_snk_io0/buffer_data/Dat*" DIFF_TERM = TRUE; • INST "<sink_instance_name>/U0/pl4_lite_snk_io0/buffer_data/Ctl" DIFF_TERM = TRUE; ...

Page 107 - Source Core Optional Constraints; I/O Standards Constraints

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 107 UG181 June 27, 2008 Source Core Optional Constraints R • * INST "TSClk*" LOC = "Bank 9"; If global clocking is used, TSClk must be placed on a pin that is connected to a global clock buffer. Using the example UCF file: • * INST "TSC...

Page 108 - Timing Ignore Constraints; User Constraints; New Target Region or Device Package

108 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 5: Constraining the Core R Timing Ignore Constraints If Source core static configuration signals are driven statically from a register, apply the timing ignore attributes (TIG) to the static configuration signals to create p...

Page 109 - Constraints Migration; Modifying the UCF File; Target Device

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 109 UG181 June 27, 2008 Constraints Migration R If the target region or device does not contain enough resources, this will result in tool errors; not due to portability issues but resource issues. Modifying the UCF File Once the target region is selected,...

Page 111 - Chapter 6; Special Design Considerations; Sink Clocking Options; Sink Core Embedded Clocking Resources

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 111 UG181 June 27, 2008 R Chapter 6 Special Design Considerations This chapter describes several design considerations to consider when designing with the Xilinx SPI-4.2 Lite core: • Clocking implementations • Multiple core implementations Sink Clocking Op...

Page 112 - User Clocking; Embedded Clocking Option

112 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 6: Special Design Considerations R User Clocking The Sink user clocking configuration allows users to fully customize the way the Sink core clocks are implemented. An example file is provided ( pl4_lite_snk_clk.v/.vhd ) that...

Page 113 - Global Clocking

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 113 UG181 June 27, 2008 Sink Clocking Options R defined in Table 2-9, page 30 . For all architectures other than Virtex-4 or Virtex-5 devices, user clocking can only be implemented using global clocking resources. When targeting the Virtex-4 and Virtex-5 d...

Page 114 - Regional Clocking; Sink User Clocking: Global Clocking

114 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 6: Special Design Considerations R . Regional Clocking This implementation uses the regional clock buffer resources BUFIO and BUFR to generate a full-rate clock ( RClk0_USER ) and inverted full-rate clock ( RDClk180_USER ). ...

Page 115 - Source Clocking Options; Sink User Clocking: Regional Clocking

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 115 UG181 June 27, 2008 Source Clocking Options R Source Clocking Options The Source core supports two clocking implementations: master clocking and slave clocking. The master clocking configuration provides a complete solution with the clock circuitry emb...

Page 116 - Source Clocking: Master and Slave Implementation

116 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 6: Special Design Considerations R cores. An example of using the Slave core to either share clock resources between Source cores or to implement a custom clocking solution is shown in Figure 6-5 . Master and slave clocking ...

Page 118 - Source Clocking: Regional Clocking for SysClk

118 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 6: Special Design Considerations R Regional Clocking For Virtex-4 and Virtex-5 device designs, this implementation uses the regional clock buffer resources BUFIO and BUFR to generate a full-rate clock ( SysClk0_GP ), an inve...

Page 119 - Slave Clocking; TSClk

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 119 UG181 June 27, 2008 Source Clocking Options R The clock implementation for SysClk and TSClk is selected in the CORE Generator GUI. Depending on the chosen clocking option, different clock resources will be used. Table 6-3 and Table 6-4 provide the cloc...

Page 120 - Multiple Core Implementations; Instantiating Multiple Cores; Sink core; Inputs; Outputs

120 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 6: Special Design Considerations R Multiple Core Implementations Using the Xilinx SPI-4.2 Lite Core, a designer can implement multiple SPI-4.2 Lite cores in a single design. Follow the guidelines below to instantiate multipl...

Page 121 - Generating the Cores; For example; Creating Top-Level UCF File

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 121 UG181 June 27, 2008 Multiple Core Implementations R ); When instantiating the cores, there are several synthesis attributes that must be included. The cores need to be defined as black boxes for the synthesis tool, and automatic insertion of IBUF or OB...

Page 122 - Clocking Considerations

122 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 6: Special Design Considerations R For each core constraints, the instance name in the UCF file must be modified to match the instance names in the top-level RTL design. For the timing and I/O pin location constraints, chang...

Page 125 - Chapter 7; Simulating and Implementing the Core; Functional Simulation; Generating a Simulation Model; Generating a Simulation Model with Initialized Calendar

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 125 UG181 June 27, 2008 R Chapter 7 Simulating and Implementing the Core The SPI-4.2 Lite core is provided as a Xilinx technology-specific netlist and simulation model. The following sections describe how to simulate and implement the SPI-4.2 Lite core in ...

Page 126 - Timing Simulation

126 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 7: Simulating and Implementing the Core R In the first method, when defining the initial values of the calendar block RAM using a COE file, the CORE Generator system converts the calendar sequence defined in the COE file int...

Page 127 - Synthesis; Synthesis of Example Design; XST

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 127 UG181 June 27, 2008 Synthesis R Before attempting timing simulation, follow the steps below to ensure that the simulator environment is properly configured. 1. Compile the Xilinx SimPrim libraries (if not already compiled). For details, see Xilinx Answ...

Page 128 - Xilinx Tool Flow; Example Design Script; NGDBuild

128 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Chapter 7: Simulating and Implementing the Core R 2. Add the necessary user source files to the project file. 3. Select target device and speed grade. 4. Synthesize the user application. Xilinx Tool Flow This section provides an ove...

Page 129 - Static Timing Analysis; Generating a Bitstream

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 129 UG181 June 27, 2008 Xilinx Tool Flow R Static Timing Analysis To evaluate timing closure on a design and create a timing report file (TWR) derived from static timing analysis of the physical design file (NCD), the trce command must be executed. The ana...

Page 131 - Appendix A; Bit

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 131 UG181 June 27, 2008 R Appendix A SPI-4.2 Lite Control Word This appendix defines the SPI-4.2 control word format as shown in Table A-1 . This table is reproduced from Table 6.2 in the OIF-SP14-02.1 specification. Table A-1: SPI-4.2 Lite Control Word Fo...

Page 133 - Appendix B

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 133 UG181 June 27, 2008 R Appendix B SPI-4.2 Lite Calendar Programming This appendix lists examples that describe how to program calendars for the Source Status FIFO and Sink Status FIFO of the SPI-4.2 Lite core. Overview In a typical application, the cale...

Page 134 - Example 3

134 www.xilinx.com SPI-4.2 Lite v4.3 User Guide UG181 June 27, 2008 Appendix B: SPI-4.2 Lite Calendar Programming R Example 3 In a OC-192c application, 1 channel requires the complete SPI-4.2 Lite bandwidth. In this case, the calendar length can be set to 1 (Calendar_Len=0). The calendar does not ha...

Page 135 - Appendix C

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 135 UG181 June 27, 2008 R Appendix C SPI-4.2 Lite Core Verification Extensive software testing with an internally developed test suite is performed for each SPI-4.2 Lite release. Using our in-house verification environment, the SPI-4.2 Lite Core was tested...

Xilinx UG181 - Manual

Table of Contents:

Summary

Other Xilinx Models