Xilinx PCI-X v5.1 - Manuals

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 9 UG158 March 24, 2008 R Preface About This Guide The Initiator/Target v5.1 for PCI-X Getting Started Guide provides information about the LogiCORE™ IP interface core for Peripheral Component Interconnect Extended (PCI-X), which provides a fully ve...

10 www.xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Preface: About This Guide R Conventions Typographical The following typographical conventions are used in this document: Convention Meaning or Use Example Courier font Messages, prompts, and program files that the system dis...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 11 UG158 March 24, 2008 Conventions R Online Document The following conventions are used in this document: Convention Meaning or Use Example Blue text Cross-reference link to a location in the current document See “Additional Resources” for details...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 13 UG158 March 24, 2008 R Chapter 1 Getting Started The Initiator/Target core for PCI-X provides a fully verified, pre-implemented PCI-X bus interface targeted for devices based on the Virtex architecture. This chapter provides information about th...

14 www.xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 1: Getting Started R Step-by-step instructions using supported design tools are provided in this guide to simulate, synthesize, and implement the Userapp example design. Additional Documentation For more information ...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 15 UG158 March 24, 2008 R Chapter 2 Licensing the Core This chapter provides instructions for installing and obtaining a license for the Initiator/Target core for PCI-X, which you must do before using it in your designs. The core is provided under ...

16 www.xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 2: Licensing the Core R Full License The Full license is provided when you purchase the core, and provides full access to all core functionality both in simulation and in hardware, including: • Gate-level functional ...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 17 UG158 March 24, 2008 R Chapter 3 Family Specific Considerations This chapter provides important design information specific to the core interface targeting Virtex devices. Design Support Table 3-1 provides a list of supported device and interfac...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 21 UG158 March 24, 2008 Device Initialization R Device Initialization Immediately after FPGA configuration, both the core interface and the user application are initialized by the startup mechanism present in all Virtex devices. During normal opera...

22 www.xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 3: Family Specific Considerations R bitstream is in use. When this occurs, external circuitry is responsible for re-initializing the FPGA and loading an alternate bitstream. This requires storage for two complete bit...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 23 UG158 March 24, 2008 Electrical Compliance R It is important to note that the frequency of this clock is not guaranteed to be constant. In fact, in a compliant system, the clock may be any frequency, up to and including the maximum allowed frequ...

24 www.xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 3: Family Specific Considerations R Input Delay Buffers Input delay buffers are used to provide guaranteed hold time on all bus inputs when in PCI bus mode. Where possible, the core interface targeting Virtex devices...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 25 UG158 March 24, 2008 Generating Bitstreams R Generating Bitstreams The bitstream generation program, bitgen, may issue DRC warnings when generating bitstreams for PCI-X designs. The number of these warnings varies depending on the configuration ...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 27 UG158 March 24, 2008 R Chapter 4 Functional Simulation This chapter describes how to simulate the Userapp example design using the supported functional simulation tools. If you are using a design with reference clocks, substitute pcix_top with p...

28 www.xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 4: Functional Simulation R ../../src/xpci/pcix_lc.v ../../src/xpci/pcix_core.v +libext+.vmd+.v -y <Xilinx Install Path>/verilog/src/unisims -y <Xilinx Install Path>/verilog/src/simprims This subset list d...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 29 UG158 March 24, 2008 Mentor Graphics ModelSim R Most of the files listed are related to the example design and its test bench. For other test benches, the following subset must be used for proper simulation of the core interface: ../source/glbl....

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 31 UG158 March 24, 2008 R Chapter 5 Synthesizing a Design This chapter describes the use of supported synthesis tools using the Userapp example design for step-by-step instructions and illustrations. If you are using a design with reference clocks,...

40 www.xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 5: Synthesizing a Design R 11. From the main project window, click Change Target to display the Options for Implementation dialog box, as shown in Figure 5-15 . 12. On the Device tab, set the Technology, Part, Speed,...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 41 UG158 March 24, 2008 Xilinx XST R Note: if you run LeonardoSpectrum with the graphical user interface, the quick setup form cannot be used to synthesize the design. Instead, choose File > Run Script from the menu. The end result of the synthe...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 43 UG158 March 24, 2008 R Chapter 6 Implementing a Design This chapter describes the use of supported FPGA implementation tools using the Userapp example design. If you are using a design with reference clocks, substitute pcix_top with pcix_top_r a...

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 45 UG158 March 24, 2008 R Chapter 7 Timing Simulation This chapter describes the use of supported timing simulation tools using the Userapp example design. If you are using a design with reference clocks, substitute pcix_top with pcix_top_r and tes...