Page 3 - Version
UG068 (v1.01) August 25, 2004 www.xilinx.com ML310 User Guide 1-800-255-7778 ML310 User Guide UG068 (v1.01) August 25, 2004 The following table shows the revision history for this document.. Version Revision 08/15/04 1.0 Initial Xilinx release. 08/25/04 1.01 Added SysACE CFGADDR details.
Page 5 - Preface: About This Manual; Foundation ISE; Chapter 2: ML310 Embedded Development Platform; Overview; Table of Contents
ML310 User Guide www.xilinx.com 5 UG068 (v1.01) August 25, 2004 1-800-255-7778 Preface: About This Manual Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK Virtex-II Pro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....
Page 7 - Preface; About This Manual; Manual Contents; Additional Resources; Resource
ML310 User Guide www.xilinx.com 7 UG068 (v1.01) August 25, 2004 1-800-255-7778 R Preface About This Manual This manual accompanies the ML310 Embedded Development System and contains information about the ML310 Hardware Platform and software tools. Manual Contents This manual contains the following c...
Page 8 - Conventions; Typographical; Courier bold
8 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter : R Conventions This document uses the following conventions. An example illustrates each convention. Typographical The following typographical conventions are used in this document: Problem Solvers Interactive to...
Page 9 - Online Document
ML310 User Guide www.xilinx.com 9 UG068 (v1.01) August 25, 2004 1-800-255-7778 R Online Document The following conventions are used in this document: Vertical ellipsis ... Repetitive material that has been omitted IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’ . . . Horizontal ellipsis . . . Repetitive ...
Page 11 - Chapter 1; Summary of Virtex-II Pro Features
ML310 User Guide www.xilinx.com 11 UG068 (v1.01) August 25, 2004 1-800-255-7778 R Chapter 1 Introduction to Virtex-II Pro, ISE, and EDK Virtex-II Pro The Virtex-II Pro Platform FPGA solution is the most technically sophisticated silicon and software product development in the history of the programm...
Page 13 - Virtex-II FPGA Fabric
ML310 User Guide www.xilinx.com 13 UG068 (v1.01) August 25, 2004 1-800-255-7778 Virtex-II Pro R • Four levels of selectable pre-emphasis • Five levels of output differential voltage • Per-channel internal loopback modes • 2.5V transceiver supply voltage Virtex-II FPGA Fabric Description of the Virte...
Page 14 - Foundation Features; Design Entry
14 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK R - 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers - Bus LVDS I/O - HyperTransport™ (LDT) I/O with current driver buffers - Built-i...
Page 15 - Synthesis
ML310 User Guide www.xilinx.com 15 UG068 (v1.01) August 25, 2004 1-800-255-7778 Foundation ISE R IP. ISE even includes technology called IP Builder, which allows you to capture your own IP and reuse it in other designs. ISE’s Architecture Wizards allow easy access to device features like the Digital...
Page 16 - Board Level Integration; Embedded Development Kit
16 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK R Board Level Integration Xilinx understands the critical issues such as complex board layout, signal integrity, high-speed bus interface, high-performance I/O bandw...
Page 17 - Chapter 2
ML310 User Guide www.xilinx.com 17 UG068 (v1.01) August 25, 2004 1-800-255-7778 R Chapter 2 ML310 Embedded Development Platform Overview The ML310 Embedded Development Platform offers designers a versatile Virtex-II Pro XC2VP30-FF896 based platform for rapid prototyping and system verification. In a...
Page 19 - Features; ML310 High-Level Block Diagram
ML310 User Guide www.xilinx.com 19 UG068 (v1.01) August 25, 2004 1-800-255-7778 Overview R Figure 2-2 shows a high-level block diagram of the ML310 and its peripherals. Features In addition to the Virtex-II Pro™ FPGA with the embedded PPC405, the ML310 board features the following: • ATX Motherboard...
Page 20 - Board Hardware; Clock Generation
20 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R ♦ 2 USB ports ♦ 2 IDE connectors ♦ GPIO ♦ SMBus Interface ♦ AC97 Audio CODEC ♦ PS/2 keyboard and mouse ports • ATX power supply Board Hardware The ML310 Virtex-II Pro FPGA...
Page 21 - DDR Memory; DDR DIMM
ML310 User Guide www.xilinx.com 21 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R II Pro FPGA I/O can be configured to use different IO standards such as SSTL2 as required on the DDR DIMM interface. Please review the ML310 Virtex-II Pro data sheet for more information regarding I/O st...
Page 22 - DDR Signaling; DDR DIMM Interface Block Diagram
22 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R DDR Signaling The FPGA DDR DIMM interface supports SSTL2 signaling. All DDR signals are controlled impedance and are SSTL2 terminated. DDR Memory Expansion The FPGA is cap...
Page 24 - Connections from FPGA to DIMM Interface, P7
24 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R ddr_dqs[5] M29 DDR_DQS02 25 ddr_dqs[6] H29 DDR_DQS01 14 ddr_dqs[7] F29 DDR_DQS00 5 ddr_dq[0] AG28 DDR_DQ63 179 ddr_dq[1] AG26 DDR_DQ62 178 ddr_dq[2] AE26 DDR_DQ61 175 ddr_...
Page 26 - Serial Port FPGA UART; Introduction to Serial Ports; Optional DDR DIMM Clocks for use with Unbuffered DIMMs
26 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R unbuffered DIMM requires more than one clock input pair versus a single clock input pair for a registered DIMM. Table 2-2 shows optional clocking connections that are requ...
Page 27 - System ACE CF Controller
ML310 User Guide www.xilinx.com 27 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R a UART usable with any member of the Virtex-II Pro device family. Please review the EDK Processor IP Reference Guide for more details. The RS-232 port directly connected to the XC2VP30 is accessible by a...
Page 28 - System ACE MPU Connection from FPGA to Controller
28 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R Non-Volatile Storage In addition to programming the FPGA and storing bitstreams, System ACE can be used for general use non-volatile storage. System ACE provides an MPU in...
Page 29 - JTAG; JTAG Connections to the XC2VP30 and System ACE
ML310 User Guide www.xilinx.com 29 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R JTAG JTAG is a simple interface that provides for many uses. On the ML310 Hardware Platform, the primary uses include configuration of the XC2VP30, debugging software (similar to the CPU debug interface)...
Page 30 - Parallel Cable IV Interface; GPIO LEDs and LCD; GPIO; PC4 IV JTAG Connector Pinout
30 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R Parallel Cable IV Interface The Parallel Cable IV (PC IV) download cable can also be used to program the XC2VP30. The pinout provided in Figure 2-7 is compatible with the ...
Page 32 - GPIO LED Interface; GPIO LCD Interface
32 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R GPIO LED Interface All LEDs connected to the GPIO lines illuminate Green when driven with a logic zero and extinguish with a logic one. Table 2-6 shows the connections for...
Page 33 - CPU Debug and CPU Trace; CPU Debug Description; GPIO LCD Control Signal Connections from FPGA to U33
ML310 User Guide www.xilinx.com 33 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R The three GPIO signals configured as outputs only are used as control signals that allows the user to read/write the LCD character display in conjunction with the eight LCD data signals defined earlier i...
Page 34 - Combined Trace/Debug Connector Pinout
34 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R The PPC405 JTAG (Joint Test Action Group) Debug port complies with IEEE standard 1149.1-1990, IEEE Standard Test Access Port and Boundary Scan Architecture. This standard ...
Page 35 - CPU Debug Connector Pinout; PCI Bus; CPU Debug Connection to XC2VP30
ML310 User Guide www.xilinx.com 35 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R CPU Debug Connector Pinout Figure 2-10 shows J12, the 16 pin header used to debug the operation of software in the CPU. This is done using debug tools such as Parallel Cable IV or third party tools. Refe...
Page 37 - PCI Bus and Device Connectivity
ML310 User Guide www.xilinx.com 37 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R Table 2-10 shows the connections for the PCI controller. Figure 2-11: PCI Bus and Device Connectivity Table 2-10: PCI Controller Connections UCF Signal Name XC2VP30 Pin (U37) Description PCI_CLK0 T2 PCI_...
Page 38 - UCF Signal Name
38 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R PCI_INTA L5 PCI Interrupt Signals PCI_INTB N2 PCI_INTC M2 PCI_INTD R9 PCI_INTE P9 PCI_INTF M3 PCI_REQ0_N P1 PCI Request Signals PCI_REQ1_N N1 PCI_REQ2_N P7 PCI_REQ3_N P8 P...
Page 41 - Parallel Port Interface, connector assembly P1
ML310 User Guide www.xilinx.com 41 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R ALi M1535D+ supports the following features: ♦ 1 parallel and 2 serial ports ♦ 2 USB ports ♦ 2 IDE connectors ♦ GPIO ♦ SMBus Interface ♦ AC97 Audio CODEC ♦ PS/2 keyboard and mouse Parallel Port Interface...
Page 42 - Serial Port Interface, connector assembly P1; ALi South Bridge Parallel Port pinout P1 (DB25)
42 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R Table 2-13 shows the ALi Parallel Port connections to P1, DB25. Serial Port Interface, connector assembly P1 In addition to the serial port accessible via the XC2VP30 FPGA...
Page 43 - USB, connector assembly J3; Signal Name
ML310 User Guide www.xilinx.com 43 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R Table 2-14 shows the RS-232 signals connected to the two DB9 connectors, P1 A/B. USB, connector assembly J3 The M1535D+ USB is an implementation of the Universal Serial Bus (USB) 1.0a specification that ...
Page 44 - IDE, connectors J15 and J16; ALi South Bridge IDE connectors, J15 and J16
44 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R IDE, connectors J15 and J16 Supports a 2-channel UltraDMA-133 IDE Master controller independently connected to a Primary 40 Pin IDC connector (J16) and a Secondary 40 Pin ...
Page 46 - Audio Jacks, J1 and J2
46 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R send byte/receive byte/ write byte/write word/read word/block read/block write command with clock synchronization function as well as 10-bit addressing ability. Please see...
Page 48 - ALi M1535 Flash Memory Interface
48 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet Controller The GD82559 10/100 Mbps Fast Ethernet controller with an integrated 10/100 Mbps physical l...
Page 49 - Introduction to IIC/SMBus
ML310 User Guide www.xilinx.com 49 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R review the GD82559 Data sheet, located on the ML310 CDROM, for more detailed information. IIC/SMBus Interface Introduction to IIC/SMBus The Inter Integrated Circuit (IIC) bus provides the connection from...
Page 50 - SMBus and IIC Controller Connections
50 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R Table 2-22 shows the FPGA connections to all SMBus and IIC devices. Table 2-22: SMBus and IIC Controller Connections UCF Signal Name XC2VP30 Pin Schem Signal Name iic_scl ...
Page 52 - SPI Signaling
52 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R Table 2-23 lists the IIC devices and their associated addresses. Serial Peripheral Interface (SPI) Introduction to SPI Serial Peripheral Interface™ (SPI), is a serial inte...
Page 53 - SPI Addressing; Push Buttons, Switches, Front Panel Interface and Jumpers; Push Buttons; System ACE Reset, SW1; SPI EEPROM Device Interface
ML310 User Guide www.xilinx.com 53 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R SPI Addressing The SPI does not use an addressed based system like the IIC Bus Interface uses. Instead, devices are selected by dedicated Slave Select signals, comparable to a Chip Select signal. Each SP...
Page 54 - System ACE Configuration Dipswitch, SW3
54 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R CPU Reset, SW2 SW2 provides a way to manually reset the powerpc system implemented in the XC2VP30. The user is responsible for connecting this signal to the PPC405 system ...
Page 55 - Front Panel Interface Connector, J23; SW3 - SysACE CFG Switch Detail
ML310 User Guide www.xilinx.com 55 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R SW3 = 0 0 0 (default) Front Panel Interface Connector, J23 The Front panel Interface connector (J23) is a 24-pin header that accepts a standard IDC 24 pin connector (0.1inch pitch). J23 provides an optio...
Page 56 - Front Panel Interface connector, J23
56 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R The front panel interface provides the following status information available at the J23 header. ♦ FPGA Configuration DONE - Output intended for driving an LED ♦ IDE Disk ...
Page 57 - Jumpers; MGT VTRX Termination Voltage Jumpers, J10 and J11
ML310 User Guide www.xilinx.com 57 UG068 (v1.01) August 25, 2004 1-800-255-7778 Board Hardware R Jumpers MGT VTRX Termination Voltage Jumpers, J10 and J11 The MGT receive termination voltage, VTRX, on the top and bottom MGTs are jumper selectable via jumpers J10 (top) and J11 (bottom). The onboard r...
Page 58 - MGT BREF Clock Selection Jumpers, J20 and J21; JTAG Source Select Jumper, J19; ATX Power Distribution and Voltage Regulation; Jumper Selection for MGT BREF clocks,J20/J21
58 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R MGT BREF Clock Selection Jumpers, J20 and J21 One of two onboard LVDS BREF clock sources, X7 or X9, can be selected via jumpers, J20 and J21. The selected clock source dri...
Page 60 - Voltage Monitor
60 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R In addition to the MC34161D voltage monitors, the ML310 employs a SMBus device, LM87, which samples several of the same supply voltages when accessed over the System Manag...
Page 62 - Personality Module Connected to ML310 Board
62 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R ML310 PM Connectors The ML310 PM connectors are Tyco Z-Dok+ connectors, part number 1367550-5. The "-5" suffix indicates a 40 pair connector. Each connector has 40...
Page 63 - PM1 Connector; PM2 Connector; Edge View of Host Board Connectors on ML310; Plastic Divider
ML310 User Guide www.xilinx.com 63 UG068 (v1.01) August 25, 2004 1-800-255-7778 High-Speed I/O R Figure 2-20 shows an edge view of the PM host board connectors on the ML310 board. Each signal pair on the PM1 and PM2 host board connectors has a wide ground pin on the opposite side of the plastic divi...
Page 64 - Adapter Board PM Connectors; ML310 PM Utility Pins; Contact Order; Adapter Board Connector Pin Detail
64 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R • 1 single-ended clock at 2.5V • 1 pin not connected Adapter Board PM Connectors Tyco Z-Dok+ adapter board connectors, part number 1367555-1 are the receptacle connectors ...
Page 65 - ML310 PM User I/O Pins
ML310 User Guide www.xilinx.com 65 UG068 (v1.01) August 25, 2004 1-800-255-7778 High-Speed I/O R PM1 Power and Ground Table 2-29 shows the power and ground pins for the PM1 connector on the ML310. PM2 Power and Ground Table 2-30 shows the power and ground pins for the PM2 connector on the ML310. ML3...
Page 66 - PM1 Pin
66 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R A11 H16 IO_L69P_0 PM_IO_82 2.5V A12 J16 IO_L69N_0 PM_IO_83 2.5V A13 A25 RXPPAD4 RXPPAD4_A25 A14 A24 RXNPAD4 RXNPAD4_A24 A15 A12 RXPPAD7 RXPPAD7_A12 A16 A11 RXNPAD7 RXNPAD7...
Page 70 - PM2 Pin
70 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004 Chapter 2: ML310 Embedded Development Platform R D14 AA5 IO_L44N_3 PM_IO_27 2.5V D15 AC4 IO_L43P_3 PM_IO_24 2.5V D16 AC3 IO_L43N_3 PM_IO_25 2.5V D17 AE4 IO_L33P_3 PM_IO_10 2.5V D18 AE3 IO_L33N_3 PM_IO_11 2.5V D19 AF4 IO_...
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