Page 3 - Date
UG081 (v6.0) June 1, 2006 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 MicroBlaze Processor Reference GuideUG081 (v6.0) June 1, 2006 The following table shows the revision history for this document. Date Version Revision 10/01/02 1.0 Xilinx EDK 3.1 release 03/11/03 2.0 Xilinx E...
Page 5 - Preface: About This Guide
UG081 (v6.0) June 1, 2006 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 Preface: About This Guide Manual Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources . . . . . . . . . . ...
Page 6 - Chapter 3: MicroBlaze Application Binary Interface
UG081 (v6.0) June 1, 2006 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MicroBlaze I/O Overview . . . . . . . . . . . . . . . . . . . . ....
Page 7 - Preface; About This Guide; Manual Contents; Resource
MicroBlaze Processor Reference Guide www.xilinx.com 7 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Preface About This Guide Welcome to the MicroBlaze Processor Reference Guide. This document providesinformation about the 32-bit soft processor MicroBlaze, which is part of the EmbeddedProcessor Developm...
Page 8 - Conventions; Typographical; Courier font; Courier bold; Italic font
8 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Preface: About This Guide R Conventions This document uses the following conventions. An example illustrates each convention. Typographical The following typographical conventions are used in this document...
Page 9 - Online Document; allow block block_name
MicroBlaze Processor Reference Guide www.xilinx.com 9 UG081 (v6.0) June 1, 2006 1-800-255-7778 Conventions R Online Document The following conventions are used in this document: Vertical ellipsis ... Repetitive material that hasbeen omitted IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’ . . . Horizontal...
Page 11 - Chapter 1; MicroBlaze Architecture; Overview; shows a functional block diagram of the MicroBlaze core.; Features; The processor ’s fixed feature set includes:; MicroBlaze Core Block Diagram
MicroBlaze Processor Reference Guide www.xilinx.com 11 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 1 MicroBlaze Architecture Overview The MicroBlaze embedded processor soft core is a reduced instruction set computer (RISC)optimized for implementation in Xilinx field programmable gate arrays (...
Page 12 - Chapter 1: MicroBlaze Architecture; Configurable Feature Overview by MicroBlaze Version
12 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R In addition to these fixed features the MicroBlaze processor is parametrized to allowselective enabling of additional functionality. Older (deprecated) versions of Mic...
Page 13 - Data Types and Endianness; Chapter 4, “MicroBlaze Instruction; Word Data Type
MicroBlaze Processor Reference Guide www.xilinx.com 13 UG081 (v6.0) June 1, 2006 1-800-255-7778 Data Types and Endianness R Data Types and Endianness MicroBlaze uses Big-Endian, bit-reversed format to represent data. The hardwaresupported data types for MicroBlaze are word, half word, and byte. The ...
Page 14 - Instruction Set Nomenclature; x bit immediate value
14 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R Table 1-5: Instruction Set Nomenclature Symbol Description Ra R0 - R31, General Purpose Register, source operand a Rb R0 - R31, General Purpose Register, source operan...
Page 15 - op1 if cond else op2
MicroBlaze Processor Reference Guide www.xilinx.com 15 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R << x Bit shift left x bits and Logic AND or Logic OR xor Logic exclusive OR op1 if cond else op2 Perform op1 if condition cond is true, else perform op2 & Concatenate. E.g. “00001...
Page 16 - Type A
16 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R ADDIKC Rd,Ra,Imm 001110 Rd Ra Imm Rd := s(Imm) + Ra + C RSUBIKC Rd,Ra,Imm 001111 Rd Ra Imm Rd := s(Imm) + Ra + C MUL Rd,Ra,Rb 010000 Rd Ra Rb 00000000000 Rd := Ra * Rb...
Page 17 - Instructions; MicroBlaze Instruction Set Summary (Continued)
MicroBlaze Processor Reference Guide www.xilinx.com 17 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R PUT Ra,FSLx 011011 00000 Ra 1000000000000 & FSLx FSLx := Ra (blocking data write) NGET Rd,FSLx 011011 Rd 00000 0100000000000 & FSLx Rd := FSLx (non-blocking data read)MSR[FSL] := 1 ...
Page 20 - Registers
20 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R Registers MicroBlaze has an orthogonal instruction set architecture. It has thirty-two 32-bit generalpurpose registers and up to seven 32-bit special purpose registers...
Page 21 - General Purpose Registers; Please refer to; Special Purpose Registers; Bits; 2-bit general purpose register
MicroBlaze Processor Reference Guide www.xilinx.com 21 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R General Purpose Registers The thirty-two 32-bit General Purpose Registers are numbered R0 through R31. Theregister file is reset on bit stream download (reset value is 0x00000000). Note: The r...
Page 22 - PC
22 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R Machine Status Register (MSR) The Machine Status Register contains control and status bits for the processor. It can beread with an MFS instruction. When reading the M...
Page 24 - EAR
24 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R Exception Address Register (EAR) The Exception Address Register stores the full load/store address that caused theexception. For an unaligned access exception that mea...
Page 25 - Exception in delay slot.
MicroBlaze Processor Reference Guide www.xilinx.com 25 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R Exception Status Register (ESR) The Exception Status Register contains status bits for the processor. When read with theMFS instruction the ESR is specified by setting Sa = 0x0005. 19 20 26 27...
Page 26 - Store Access Exception; Source/Destination Register
26 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R Branch Target Register (BTR) The Branch Target Register only exists if the MicroBlaze processor is configured to useexceptions. The register stores the branch target a...
Page 31 - Pipeline Architecture
MicroBlaze Processor Reference Guide www.xilinx.com 31 UG081 (v6.0) June 1, 2006 1-800-255-7778 Pipeline Architecture R Pipeline Architecture MicroBlaze instruction execution is pipelined. The pipeline is divided into five stages:Fetch (IF), Decode (OF), Execute (EX), Access Memory (MEM), and Writeb...
Page 32 - Branches; Delay Slots; Memory Architecture; For details on the different memory interfaces please refer to
32 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R Branches Normally the instructions in the fetch and decode stages (as well as prefetch buffer) areflushed when executing a taken branch. The fetch pipeline stage is th...
Page 33 - Vectors and Return Address Register File Location
MicroBlaze Processor Reference Guide www.xilinx.com 33 UG081 (v6.0) June 1, 2006 1-800-255-7778 Reset, Interrupts, Exceptions, and Break R Reset, Interrupts, Exceptions, and Break MicroBlaze supports reset, interrupt, user exception, break, and hardware exceptions. Thefollowing section describes the...
Page 34 - Reset; Equivalent Pseudocode; Hardware Exceptions; Exception Causes
34 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R Reset When a Reset or Debug_Rst (1) occurs, MicroBlaze will flush the pipeline and start fetching instructions from the reset vector (address 0x0). Both external reset...
Page 35 - Breaks; Hardware Breaks
MicroBlaze Processor Reference Guide www.xilinx.com 35 UG081 (v6.0) June 1, 2006 1-800-255-7778 Reset, Interrupts, Exceptions, and Break R • Unaligned Exception The unaligned exception is caused by a word access where the address to the data bushas bits 30 or 31 set, or a half-word access with bit 3...
Page 36 - Interrupt
36 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R Software Breaks To perform a software break, use the brk and brki instructions. Refer to Chapter 4, “MicroBlaze Instruction Set Architecture” for detailed information ...
Page 37 - Instruction Cache; Instruction Cache Organization
MicroBlaze Processor Reference Guide www.xilinx.com 37 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instruction Cache R PC ← 0x00000008 Instruction Cache Overview MicroBlaze may be used with an optional instruction cache for improved performancewhen executing code that resides outside the LMB address ra...
Page 38 - Instruction Cache Operation; MSR Bit; Chapter 4, “MicroBlaze Instruction Set Architecture”; Data Cache; The data cache has the following features
38 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R For example: in a MicroBlaze configured with C_ICACHE_BASEADDR= 0x00300000,C_ICACHE_HIGHADDR=0x0030ffff, C_CACHE_BYTE_SIZE=4096, andC_ICACHE_LINELEN=8; the cacheable m...
Page 39 - General Data Cache Functionality; Data Cache Organization
MicroBlaze Processor Reference Guide www.xilinx.com 39 UG081 (v6.0) June 1, 2006 1-800-255-7778 Data Cache R • Cache on and off controlled using a bit in the MSR • Optional WDC instruction to invalidate data cache lines General Data Cache Functionality When the data cache is used, the memory address...
Page 40 - Data Cache Software Support; The contents of the cache is preserved when the cache is disabled.; WDC Instruction; The MicroBlaze floating point unit is based on the
40 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R A load from an address within the cacheable range will, provided that the cache is enabled,trigger a check to determine if the requested data is currently cached. If i...
Page 41 - Format; -bit biased exponent; Rounding; “General Purpose Registers”; Arithmetic; The FPU implements the following floating point operations:; IEEE 754 Single Precision format
MicroBlaze Processor Reference Guide www.xilinx.com 41 UG081 (v6.0) June 1, 2006 1-800-255-7778 Floating Point Unit (FPU) R Format An IEEE 754 single precision floating point number is composed of the following threefields: 1. 1-bit sign 2. 8-bit biased exponent 3. 23-bit fraction (a.k.a. mantissa o...
Page 42 - Comparison; The FPU implements the following floating point comparisons:; Exceptions; get; Hardware Acceleration using FSL
42 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Architecture R Comparison The FPU implements the following floating point comparisons: • compare less-than, fcmp.lt • compare equal, fcmp.eq • compare less-or-equal, fcmp.le • compar...
Page 43 - Debug and Trace; Debug Overview; Support for multiple processors; Trace Overview; MicroBlaze; FSLx; FSLx
MicroBlaze Processor Reference Guide www.xilinx.com 43 UG081 (v6.0) June 1, 2006 1-800-255-7778 Debug and Trace R Figure 1-12: FSL used with HW accelerated function f x This method is similar to extending the ISA with custom instructions, but has the benefit ofnot making the overall speed of the pro...
Page 45 - Chapter 2; MicroBlaze Signal Interface Description; MicroBlaze I/O Overview
MicroBlaze Processor Reference Guide www.xilinx.com 45 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 2 MicroBlaze Signal Interface Description Overview The MicroBlaze core is organized as a Harvard architecture with separate bus interfaceunits for data accesses and instruction accesses. The fol...
Page 46 - Chapter 2: MicroBlaze Signal Interface Description; Summary of MicroBlaze Core I/O
46 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Figure 2-1: MicroBlaze Core Block Diagram DXCL_M DXCL_S Data-side Instruction-side DOPB DLMB IOPB ILMB bus interface bus interface Instruction Buffer P...
Page 48 - Signal
48 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R On-Chip Peripheral Bus (OPB) Interface Description The MicroBlaze OPB interfaces are implemented as byte-enable capable masters. Pleaserefer to the Xil...
Page 49 - Local Memory Bus (LMB) Interface Description; LMB Signal Interface; not used
MicroBlaze Processor Reference Guide www.xilinx.com 49 UG081 (v6.0) June 1, 2006 1-800-255-7778 Local Memory Bus (LMB) Interface Description R Local Memory Bus (LMB) Interface Description The LMB is a synchronous bus used primarily to access on-chip block RAM. It uses aminimum number of control sign...
Page 50 - AS; Byte Lanes Used
50 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Data_Write[0:31] The write data bus is an output from the core and contains the data that is written tomemory. It becomes valid when AS is high and goe...
Page 51 - LMB Transactions; Generic Write Operation; LMB Generic Write Operation
MicroBlaze Processor Reference Guide www.xilinx.com 51 UG081 (v6.0) June 1, 2006 1-800-255-7778 Local Memory Bus (LMB) Interface Description R LMB Transactions The following diagrams provide examples of LMB bus operations. Generic Write Operation Generic Read Operation Figure 2-2: LMB Generic Write ...
Page 52 - LMB Single Cycle Back-to-Back Read Operation
52 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Back-to-Back Write Operation Single Cycle Back-to-Back Read Operation Back-to-Back Mixed Read/Write Operation Figure 2-4: LMB Back-to-Back Write Operat...
Page 53 - Read and Write Data Steering
MicroBlaze Processor Reference Guide www.xilinx.com 53 UG081 (v6.0) June 1, 2006 1-800-255-7778 Local Memory Bus (LMB) Interface Description R Read and Write Data Steering The MicroBlaze data-side bus interface performs the read steering and write steeringrequired to support the following transfers:...
Page 54 - Fast Simplex Link (FSL) Interface Description; Master FSL Signal Interface
54 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Fast Simplex Link (FSL) Interface Description The Fast Simplex Link bus provides a point-to-point communication channel between anoutput FIFO and an in...
Page 55 - FSL Transactions; FSL BUS Write Operation; Xilinx CacheLink (XCL) Interface Description; cache used in this example); Memory; Schematic
MicroBlaze Processor Reference Guide www.xilinx.com 55 UG081 (v6.0) June 1, 2006 1-800-255-7778 Xilinx CacheLink (XCL) Interface Description R FSL Transactions FSL BUS Write Operation A write to the FSL bus is performed by MicroBlaze using one of the flavors of the putinstruction. A write operations...
Page 56 - CacheLink Signal Interface; MicroBlaze Cache Link signals
56 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R The MicroBlaze CacheLink interface can also connect to an Fast Simplex Link (FSL)interfaced memory controller via explicitly instantiated FSL master/sl...
Page 57 - CacheLink Transactions
MicroBlaze Processor Reference Guide www.xilinx.com 57 UG081 (v6.0) June 1, 2006 1-800-255-7778 Xilinx CacheLink (XCL) Interface Description R CacheLink Transactions All individual CacheLink accesses follow the FSL FIFO based transaction protocol: • Access information is encoded over the FSL data an...
Page 58 - Instruction Cache Read Miss; Data Cache Read Miss; Write the word aligned; Data Cache Write
58 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R The CacheLink solution uses one incoming (slave) and one outgoing (master) FSL percache controller. The outgoing FSL is used to send access requests, w...
Page 59 - Debug Interface Description
MicroBlaze Processor Reference Guide www.xilinx.com 59 UG081 (v6.0) June 1, 2006 1-800-255-7778 Debug Interface Description R 0b01=byte1 or halfword0, 0x10=byte2, and 0x11=byte3 or halfword1. The selection ofhalf-word or byte access is based on the control bit for the data word in step 4. 3. If DCAC...
Page 60 - MicroBlaze Trace signals
60 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Trace_Reg_Write 1 Instruction writes to theregister file std_logic output Trace_Reg_Addr 1 Destination registeraddress std_logic_vector(0 to 4) output ...
Page 61 - MicroBlaze Core Configurability
MicroBlaze Processor Reference Guide www.xilinx.com 61 UG081 (v6.0) June 1, 2006 1-800-255-7778 MicroBlaze Core Configurability R MicroBlaze Core Configurability The MicroBlaze core has been developed to support a high degree of user configurability.This allows tailoring of the processor to meet spe...
Page 65 - Chapter 3; Scope; Data types in MicroBlaze assembly programs
MicroBlaze Processor Reference Guide www.xilinx.com 65 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 3 MicroBlaze Application BinaryInterface Scope This document describes MicroBlaze Application Binary Interface (ABI), which isimportant for developing software in assembly language for the soft ...
Page 66 - Register Usage Conventions; Register usage conventions
66 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 3: MicroBlaze Application Binary Interface R Register Usage Conventions The register usage convention for MicroBlaze is given in Table 3-2 . The architecture for MicroBlaze defines 32 general purp...
Page 67 - “MicroBlaze Application Binary Interface”; Stack Convention
MicroBlaze Processor Reference Guide www.xilinx.com 67 UG081 (v6.0) June 1, 2006 1-800-255-7778 Stack Convention R • Certain registers are used as dedicated registers and programmers are not expected touse them for any other purpose. ♦ Registers R14 through R17 are used for storing the return addres...
Page 69 - Calling Convention; Refer to; Memory Model; Small data area
MicroBlaze Processor Reference Guide www.xilinx.com 69 UG081 (v6.0) June 1, 2006 1-800-255-7778 Memory Model R Figure 3-2: Stack Frame Calling Convention The caller function passes parameters to the callee function using either the registers (R5through R10) or on its own stack frame. The callee uses...
Page 70 - Interrupt and Exception Handling; Code for passing control to exception and interrupt handlers
70 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 3: MicroBlaze Application Binary Interface R Interrupt and Exception Handling MicroBlaze assumes certain address locations for handling interrupts and exceptions asindicated in Table 3-3 . At thes...
Page 71 - Chapter 4; MicroBlaze Instruction Set Architecture; Summary; Symbol notation; rx
MicroBlaze Processor Reference Guide www.xilinx.com 71 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 4 MicroBlaze Instruction Set Architecture Summary This chapter provides a detailed guide to the Instruction Set Architecture of MicroBlaze™. Notation The symbols used throughout this document ar...
Page 72 - Chapter 4: MicroBlaze Instruction Set Architecture; Formats
72 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R Formats MicroBlaze uses two instruction formats: Type A and Type B. Type A Type A is used for register-register instructions. It contains the opcode, o...
Page 73 - Arithmetic Add; Description; Registers Altered; rD; Latency; cycle; Note; add
MicroBlaze Processor Reference Guide www.xilinx.com 73 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R add Arithmetic Add Description The sum of the contents of registers rA and rB, is placed into register rD. Bit 3 of the instruction (labeled as K in the figure) is set to a one for the mnem...
Page 74 - Arithmetic Add Immediate; Notes; addi
74 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R addi Arithmetic Add Immediate Description The sum of the contents of registers rA and the value in the IMM field, sign-extended to 32bits, is placed in...
Page 75 - Logical AND; and
MicroBlaze Processor Reference Guide www.xilinx.com 75 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R and Logical AND Description The contents of register rA are ANDed with the contents of register rB; the result is placedinto register rD. Pseudocode (rD) ← (rA) ∧ (rB) Registers Altered • r...
Page 76 - Logial AND with Immediate; andi
76 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R andi Logial AND with Immediate Description The contents of register rA are ANDed with the value of the IMM field, sign-extended to 32bits; the result i...
Page 77 - Logical AND NOT; andn
MicroBlaze Processor Reference Guide www.xilinx.com 77 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R andn Logical AND NOT Description The contents of register rA are ANDed with the logical complement of the contents ofregister rB; the result is placed into register rD. Pseudocode (rD) ← (r...
Page 78 - Logical AND NOT with Immediate; andni
78 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R andni Logical AND NOT with Immediate Description The IMM field is sign-extended to 32 bits. The contents of register rA are ANDed with thelogical compl...
Page 79 - Branch if Equal; beq; Branch if Equal; beqd; Branch if Equal with Delay
MicroBlaze Processor Reference Guide www.xilinx.com 79 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R beq Branch if Equal Description Branch if rA is equal to 0, to the instruction located in the offset value of rB. The target ofthe branch will be the instruction at address PC + rB. The mne...
Page 80 - Branch Immediate if Equal; Branch Immediate if Equal; beqid; Branch Immediate if Equal with Delay
80 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R beqi Branch Immediate if Equal Description Branch if rA is equal to 0, to the instruction located in the offset value of IMM. The targetof the branch w...
Page 81 - Branch if Greater or Equal; Branch if Greater or Equal; bged; Branch if Greater or Equal with Delay
MicroBlaze Processor Reference Guide www.xilinx.com 81 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bge Branch if Greater or Equal Description Branch if rA is greater or equal to 0, to the instruction located in the offset value of rB. Thetarget of the branch will be the instruction at ad...
Page 82 - Branch Immediate if Greater or Equal; Branch Immediate if Greater or Equal; bgeid; Branch Immediate if Greater or Equal with Delay
82 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R bgei Branch Immediate if Greater or Equal Description Branch if rA is greater or equal to 0, to the instruction located in the offset value of IMM.The ...
Page 83 - Branch if Greater Than; Branch if Greater Than; bgtd; Branch if Greater Than with Delay
MicroBlaze Processor Reference Guide www.xilinx.com 83 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bgt Branch if Greater Than Description Branch if rA is greater than 0, to the instruction located in the offset value of rB. The targetof the branch will be the instruction at address PC + ...
Page 84 - Branch Immediate if Greater Than; Branch Immediate if Greater Than; bgtid; Branch Immediate if Greater Than with Delay
84 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R bgti Branch Immediate if Greater Than Description Branch if rA is greater than 0, to the instruction located in the offset value of IMM. Thetarget of t...
Page 85 - Branch if Less or Equal; Branch if Less or Equal; bled; Branch if Less or Equal with Delay
MicroBlaze Processor Reference Guide www.xilinx.com 85 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R ble Branch if Less or Equal Description Branch if rA is less or equal to 0, to the instruction located in the offset value of rB. Thetarget of the branch will be the instruction at address ...
Page 86 - Branch Immediate if Less or Equal; Branch Immediate if Less or Equal; bleid; Branch Immediate if Less or Equal with Delay
86 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R blei Branch Immediate if Less or Equal Description Branch if rA is less or equal to 0, to the instruction located in the offset value of IMM. Thetarget...
Page 87 - Branch if Less Than; Branch if Less Than; bltd; Branch if Less Than with Delay
MicroBlaze Processor Reference Guide www.xilinx.com 87 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R blt Branch if Less Than Description Branch if rA is less than 0, to the instruction located in the offset value of rB. The target ofthe branch will be the instruction at address PC + rB. Th...
Page 88 - Branch Immediate if Less Than; Branch Immediate if Less Than; bltid; Branch Immediate if Less Than with Delay
88 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R blti Branch Immediate if Less Than Description Branch if rA is less than 0, to the instruction located in the offset value of IMM. The targetof the bra...
Page 89 - Branch if Not Equal; bne; Branch if Not Equal; bned; Branch if Not Equal with Delay
MicroBlaze Processor Reference Guide www.xilinx.com 89 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bne Branch if Not Equal Description Branch if rA not equal to 0, to the instruction located in the offset value of rB. The target ofthe branch will be the instruction at address PC + rB. Th...
Page 90 - Branch Immediate if Not Equal; Branch Immediate if Not Equal; bneid; Branch Immediate if Not Equal with Delay
90 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R bnei Branch Immediate if Not Equal Description Branch if rA not equal to 0, to the instruction located in the offset value of IMM. The targetof the bra...
Page 91 - br; Unconditional Branch; Branch to the instruction located at address determined by rB.; Pseudocode
MicroBlaze Processor Reference Guide www.xilinx.com 91 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R br Unconditional Branch Description Branch to the instruction located at address determined by rB. The mnemonics brld and brald will set the L bit. If the L bit is set, linking will beperfo...
Page 92 - The instructions brl and bral are not available.
92 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R Note The instructions brl and bral are not available. A delay slot must not be used by the following: IMM, branch, or break instructions. Thisalso appl...
Page 93 - bri; Unconditional Branch Immediate
MicroBlaze Processor Reference Guide www.xilinx.com 93 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bri Unconditional Branch Immediate Description Branch to the instruction located at address determined by IMM, sign-extended to 32 bits. The mnemonics brlid and bralid will set the L bit. I...
Page 94 - The instructions brli and brali are not available.
94 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R Notes The instructions brli and brali are not available. By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32b...
Page 95 - Break; cycles; brk
MicroBlaze Processor Reference Guide www.xilinx.com 95 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R brk Break Description Branch and link to the instruction located at address value in rB. The current value of PCwill be stored in rD. The BIP flag in the MSR will be set. Pseudocode (rD) ← ...
Page 96 - Break Immediate; brki
96 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R brki Break Immediate Description Branch and link to the instruction located at address value in IMM, sign-extended to 32bits. The current value of PC w...
Page 97 - Barrel Shift; bsrl; Barrel Shift Right Logical; bsra; Barrel Shift Right Arithmetical; bsll; Barrel Shift Left Logical
MicroBlaze Processor Reference Guide www.xilinx.com 97 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bs Barrel Shift Description Shifts the contents of register rA by the amount specified in register rB and puts the resultin register rD. The mnemonic bsll sets the S bit (Side bit). If the ...
Page 98 - bsi; Barrel Shift Immediate; bsrli; Barrel Shift Right Logical Immediate; bsrai; Barrel Shift Right Arithmetical Immediate; bslli; Barrel Shift Left Logical Immediate
98 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R bsi Barrel Shift Immediate Description Shifts the contents of register rA by the amount specified by IMM and puts the result inregister rD. The mnemoni...
Page 99 - Integer Compare; cmp
MicroBlaze Processor Reference Guide www.xilinx.com 99 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R cmp Integer Compare Description The contents of register rA is subtracted from the contents of register rB and the result isplaced into register rD. The MSB bit of rD is adjusted to shown t...
Page 100 - Floating Point Arithmetic Add; cycles; fadd
100 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R fadd Floating Point Arithmetic Add Description The floating point sum of registers rA and rB, is placed into register rD. Pseudocode if isDnz(rA) or i...
Page 101 - Reverse Floating Point Arithmetic Subtraction; frsub
MicroBlaze Processor Reference Guide www.xilinx.com 101 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R frsub Reverse Floating Point Arithmetic Subtraction Description The floating point value in rA is subtracted from the floating point value in rB and theresult is placed into register rD. P...
Page 102 - Floating Point Arithmetic Multiplication; fmul
102 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R fmul Floating Point Arithmetic Multiplication Description The floating point value in rA is multiplied with the floating point value in rB and theresu...
Page 103 - Floating Point Arithmetic Division; fdiv
MicroBlaze Processor Reference Guide www.xilinx.com 103 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R fdiv Floating Point Arithmetic Division Description The floating point value in rB is divided by the floating point value in rA and the result isplaced into register rD. Pseudocode if isDn...
Page 104 - fcmp; Floating Point Number Comparison; OpSel; Floating Point Comparison Operation
104 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R fcmp Floating Point Number Comparison Description The floating point value in rB is compared with the floating point value in rA and thecomparison res...
Page 106 - get from fsl interface; The get instruction has four variants.
106 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R get get from fsl interface Description MicroBlaze will read from the FSLx interface and place the result in register rD. The get instruction has four ...
Page 107 - Integer Divide; idiv
MicroBlaze Processor Reference Guide www.xilinx.com 107 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R idiv Integer Divide Description The contents of register rB is divided by the contents of register rA and the result is placedinto register rD. If the U bit is set, rA and rB is considered...
Page 108 - Immediate; imm; IMM
108 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R imm Immediate Description The instruction imm loads the IMM value into a temporary register. It also locks this valueso it can be used by the followin...
Page 109 - Load Byte Unsigned; lbu
MicroBlaze Processor Reference Guide www.xilinx.com 109 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R lbu Load Byte Unsigned Description Loads a byte (8 bits) from the memory location that results from adding the contents ofregisters rA and rB. The data is placed in the least significant b...
Page 110 - Load Byte Unsigned Immediate; lbui
110 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R lbui Load Byte Unsigned Immediate Description Loads a byte (8 bits) from the memory location that results from adding the contents ofregister rA with ...
Page 111 - Load Halfword Unsigned; lhu
MicroBlaze Processor Reference Guide www.xilinx.com 111 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R lhu Load Halfword Unsigned Description Loads a halfword (16 bits) from the halfword aligned memory location that results fromadding the contents of registers rA and rB. The data is placed ...
Page 112 - Load Halfword Unsigned Immediate; lhui
112 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R lhui Load Halfword Unsigned Immediate Description Loads a halfword (16 bits) from the halfword aligned memory location that results fromadding the con...
Page 113 - Load Word; lw
MicroBlaze Processor Reference Guide www.xilinx.com 113 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R lw Load Word Description Loads a word (32 bits) from the word aligned memory location that results from addingthe contents of registers rA and rB. The data is placed in register rD. Pseudo...
Page 114 - Load Word Immediate; lwi
114 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R lwi Load Word Immediate Description Loads a word (32 bits) from the word aligned memory location that results from addingthe contents of register rA a...
Page 115 - Move From Special Purpose Register; mfs
MicroBlaze Processor Reference Guide www.xilinx.com 115 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R mfs Move From Special Purpose Register Description Copies the contents of the special purpose register rS into register rD. Pseudocode switch (rS): case 0x0000 : (rD) ← PC case 0x0001 : (r...
Page 116 - Read MSR and clear bits in MSR; The immediate values has to be less than 2; msrclr
116 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R msrclr Read MSR and clear bits in MSR Description Copies the contents of the special purpose register MSR into register rD.Bit positions in the IMM va...
Page 117 - Read MSR and set bits in MSR; msrset
MicroBlaze Processor Reference Guide www.xilinx.com 117 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R msrset Read MSR and set bits in MSR Description Copies the contents of the special purpose register MSR into register rD.Bit positions in the IMM value that are 1 are set in the MSR. Bit p...
Page 118 - Move To Special Purpose Register; Copies the contents of register rD into the MSR or FSR.; rS; The PC, ESR and EAR cannot be written by the MTS instruction.; mts
118 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R mts Move To Special Purpose Register Description Copies the contents of register rD into the MSR or FSR. Pseudocode (rS) ← (rA) Registers Altered • rS...
Page 119 - Multiply; mul
MicroBlaze Processor Reference Guide www.xilinx.com 119 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R mul Multiply Description Multiplies the contents of registers rA and rB and puts the result in register rD. This is a 32-bit by 32-bit multiplication that will produce a 64-bit result. The...
Page 120 - Multiply Immediate; muli
120 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R muli Multiply Immediate Description Multiplies the contents of registers rA and the value IMM, sign-extended to 32 bits; andputs the result in registe...
Page 121 - Logical OR; or
MicroBlaze Processor Reference Guide www.xilinx.com 121 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R or Logical OR Description The contents of register rA are ORed with the contents of register rB; the result is placedinto register rD. Pseudocode (rD) ← (rA) ∨ (rB) Registers Altered • rD ...
Page 122 - Logical OR with Immediate; ori
122 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R ori Logical OR with Immediate Description The contents of register rA are ORed with the extended IMM field, sign-extended to 32bits; the result is pla...
Page 123 - Pattern Compare Byte Find; If none of the byte pairs match, rD is set to 0; pcmpbf
MicroBlaze Processor Reference Guide www.xilinx.com 123 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R pcmpbf Pattern Compare Byte Find Description The contents of register rA is bytewise compared with the contents in register rB. • rD is loaded with the position of the first matching byte ...
Page 124 - Pattern Compare Equal; rD is loaded with 1 if they match, and 0 if not; pcmpeq
124 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R pcmpeq Pattern Compare Equal Description The contents of register rA is compared with the contents in register rB. • rD is loaded with 1 if they match...
Page 125 - Pattern Compare Not Equal; rD is loaded with 0 if they match, and 1 if not; pcmpne
MicroBlaze Processor Reference Guide www.xilinx.com 125 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R pcmpne Pattern Compare Not Equal Description The contents of register rA is compared with the contents in register rB. • rD is loaded with 0 if they match, and 1 if not Pseudocode if (rB) ...
Page 126 - put to fsl interface; The put instruction has four variants.; put
126 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R put put to fsl interface Description MicroBlaze will write the value from register rA to the FSLx interface. The put instruction has four variants. Th...
Page 127 - Arithmetic Reverse Subtract; rsub
MicroBlaze Processor Reference Guide www.xilinx.com 127 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R rsub Arithmetic Reverse Subtract Description The contents of register rA is subtracted from the contents of register rB and the result isplaced into register rD. Bit 3 of the instruction (...
Page 128 - rsubi; Arithmetic Reverse Subtract Immediate; When the Carry is set by a subtraction, it means that
128 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R rsubi Arithmetic Reverse Subtract Immediate Description The contents of register rA is subtracted from the value of IMM, sign-extended to 32 bits,and ...
Page 129 - Return from Break; cycles; Convention is to use general purpose register r16 as rA.; rtbd
MicroBlaze Processor Reference Guide www.xilinx.com 129 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R rtbd Return from Break rn from Interrupt Description Return from break will branch to the location specified by the contents of rA plus the IMMfield, sign-extended to 32 bits. It will also...
Page 130 - Return from Interrupt; Convention is to use general purpose register r14 as rA.; rtid
130 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R rtid Return from Interrupt rn from Interrupt Description Return from interrupt will branch to the location specified by the contents of rA plus theIMM...
Page 131 - Return from Exception; rted
MicroBlaze Processor Reference Guide www.xilinx.com 131 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R rted Return from Exception Description Return from exception will branch to the location specified by the contents of rA plus theIMM field, sign-extended to 32 bits. The instruction will a...
Page 132 - Return from Subroutine; Convention is to use general purpose register r15 as rA.; rtsd
132 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R rtsd Return from Subroutine Description Return from subroutine will branch to the location specified by the contents of rA plus theIMM field, sign-ext...
Page 133 - Store Byte; None; sb
MicroBlaze Processor Reference Guide www.xilinx.com 133 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sb Store Byte Description Stores the contents of the least significant byte of register rD, into the memory location thatresults from adding the contents of registers rA and rB. Pseudocode...
Page 134 - Store Byte Immediate; sbi
134 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R sbi Store Byte Immediate Description Stores the contents of the least significant byte of register rD, into the memory location thatresults from addin...
Page 135 - Sign Extend Halfword
MicroBlaze Processor Reference Guide www.xilinx.com 135 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sext16 Sign Extend Halfword Description This instruction sign-extends a halfword (16 bits) into a word (32 bits). Bit 16 in rA will becopied into bits 0-15 of rD. Bits 16-31 in rA will be ...
Page 137 - Store Halfword; sh
MicroBlaze Processor Reference Guide www.xilinx.com 137 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sh Store Halfword Description Stores the contents of the least significant halfword of register rD, into the halfwordaligned memory location that results from adding the contents of regist...
Page 138 - Store Halfword Immediate; shi
138 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R shi Store Halfword Immediate Description Stores the contents of the least significant halfword of register rD, into the halfwordaligned memory locatio...
Page 139 - Shift Right Arithmetic; sra
MicroBlaze Processor Reference Guide www.xilinx.com 139 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sra Shift Right Arithmetic Description Shifts arithmetically the contents of register rA, one bit to the right, and places the result inrD. The most significant bit of rA (i.e. the sign bi...
Page 140 - Shift Right with Carry; src
140 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R src Shift Right with Carry Description Shifts the contents of register rA, one bit to the right, and places the result in rD. The Carryflag is shifted...
Page 141 - Shift Right Logical; srl
MicroBlaze Processor Reference Guide www.xilinx.com 141 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R srl Shift Right Logical Description Shifts logically the contents of register rA, one bit to the right, and places the result in rD.A zero is shifted in the shift chain and placed in the m...
Page 142 - Store Word; sw
142 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R sw Store Word Description Stores the contents of register rD, into the word aligned memory location that results fromadding the contents of registers ...
Page 143 - Store Word Immediate; Register Altered; swi
MicroBlaze Processor Reference Guide www.xilinx.com 143 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R swi Store Word Immediate Description Stores the contents of register rD, into the word aligned memory location that results fromadding the contents of registers rA and the value IMM, sign-...
Page 144 - Write to Data Cache; wdc
144 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R wdc Write to Data Cache Description Write into the data cache tag. The register rB value is not used. Register rA contains theinstruction address. Bit...
Page 145 - Write to Instruction Cache; wic
MicroBlaze Processor Reference Guide www.xilinx.com 145 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R wic Write to Instruction Cache Description Write into the instruction cache tag. The register rB value is not used. Register rA containsthe instruction address. Bit 30 in rA is the new val...
Page 146 - Logical Exclusive OR; xor
146 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Architecture R xor Logical Exclusive OR Description The contents of register rA are XORed with the contents of register rB; the result is placedinto register rD. Pse...
Page 147 - Logical Exclusive OR with Immediate; xori
MicroBlaze Processor Reference Guide www.xilinx.com 147 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R xori Logical Exclusive OR with Immediate Description The IMM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents ofregister rA are XORed with the extended IMM...
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