Xilinx UG492 - Manuals

6 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 14: Quick Start Example Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Generating the Core . . . . . . . . . . . . . ...

Ethernet AVB Endpoint User Guide www.xilinx.com 7 UG492 July 23, 2010 Chapter 16: Detailed Example Design (EDK format) Directory and File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 <project directory> . . . . . . . . . . . . . ....

Ethernet AVB Endpoint User Guide www.xilinx.com 9 UG492 July 23, 2010 Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Overview of Ethernet Audio Video Bridging Figure 3-1: Example AVB Home Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fig...

Ethernet AVB Endpoint User Guide www.xilinx.com 11 UG492 July 23, 2010 Chapter 16: Detailed Example Design (EDK format) Appendix A: RTC Time Stamp Accuracy Figure A-1: RTC Periodic Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure A-2: R...

Ethernet AVB Endpoint User Guide www.xilinx.com 13 UG492 July 23, 2010 Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Overview of Ethernet Audio Video Bridging Chapter 4: Generating the Core Table 4-1: XCO File Values and Default Values . . . . . . . . . . . . . . . . . . . . . . ....

14 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Table 10-7: Seconds Field Offset bits [31:0] (PLB_base_address + 0x2808) . . . . . . . . . . . . 95 Table 10-8: Seconds Field Offset bits [47:32] (PLB_base_address + 0x280C) . . . . . . . . . . 95 Table 10-9: RTC Increment Value ...

Ethernet AVB Endpoint User Guide www.xilinx.com 17 UG492 July 23, 2010 Preface About This Guide The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx ...

18 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Preface: About This Guide • Chapter 13, “Software Drivers” describes the function of the software drivers delivered with the core. • Chapter 14, “Quick Start Example Design”Chapter 3, “Quick Start Example Design” provides instruc...

Ethernet AVB Endpoint User Guide www.xilinx.com 19 UG492 July 23, 2010 Conventions Online Document The following conventions are used in this document: Braces { } A list of items from which you must choose one or more lowpwr = { on | off } Vertical bar | Separates items in a list of choices lowpwr =...

20 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Preface: About This Guide List of Abbreviations The following table describes acronyms used in this manual. Acronym Spelled Out AV Audio Video AVB Audio Video Bridging BMCA Best Master Clock Algorithm CRC Cyclic Redundancy Check ...

Ethernet AVB Endpoint User Guide www.xilinx.com 23 UG492 July 23, 2010 Chapter 1 Introduction This chapter introduces the core and provides related information including recommended design experience, additional resources, technical support, and how to submit feedback to Xilinx. The Ethernet AVB End...

24 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 1: Introduction Recommended Design Experience Although the Ethernet AVB Endpoint core is a fully verified solution, the challenge associated with implementing a complete design varies depending on the configuration and fu...

Ethernet AVB Endpoint User Guide www.xilinx.com 25 UG492 July 23, 2010 Feedback Document For comments or suggestions about this document, submit a WebCase from www.xilinx.com/support/clearexpress/websupport.htm/ Be sure to include the following information: • Document title • Document number • Page ...

Ethernet AVB Endpoint User Guide www.xilinx.com 27 UG492 July 23, 2010 Chapter 2 Licensing the Core This chapter provides instructions for obtaining a license key for the Ethernet AVB Endpoint core, which you must do before using the core in your designs. The Ethernet AVB Endpoint core is provided u...

28 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 2: Licensing the Core Full The Full license key is available when you purchase a license for the core and provides full access to all core functionality both in simulation and in hardware, including: • Functional simulati...

Ethernet AVB Endpoint User Guide www.xilinx.com 29 UG492 July 23, 2010 Chapter 3 Overview of Ethernet Audio Video Bridging Figure 3-1 illustrates a potential home network, consisting of wired (ethernet) and wireless components, which utilize the technology being defined by the IEEE802.1 Audio Video ...

30 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 3: Overview of Ethernet Audio Video Bridging To understand the requirements of this network, we must differentiate between certain types of data: • Audio and Video streaming data , referred to in this document as AV traff...

Ethernet AVB Endpoint User Guide www.xilinx.com 31 UG492 July 23, 2010 AVB Specifications P802.1Qav This specification defines the mechanism for queuing and forwarding AV traffic from a talker to a listener across the network. This can involve several network hops (network bridge devices that the da...

32 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 3: Overview of Ethernet Audio Video Bridging P802.1Qat This specification defines a Stream Reservation Protocol (SRP) which must be used over the AVB network. Every listener that intends to receive audio/video AV traffic ...

Ethernet AVB Endpoint User Guide www.xilinx.com 35 UG492 July 23, 2010 Chapter 4 Generating the Core The Ethernet AVB Endpoint core is fully configurable using the CORE Generator™ software, which provides a Graphical User Interface (GUI) for defining parameters and options. For help starting and usi...

36 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 4: Generating the Core Component Name The component name is used as the base name of the output files generated for the core. Names must begin with a letter and must be composed from the following characters: a through z,...

Ethernet AVB Endpoint User Guide www.xilinx.com 37 UG492 July 23, 2010 Ethernet AVB GUI Page 2 Ethernet AVB GUI Page 2 Figure 4-2 shows page 2 of the Ethernet AVB Endpoint GUI customization screen. This page provides options for configuring the “PLB Interface” of the core. This option is only requir...

38 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 4: Generating the Core Parameter Values in the XCO File XCO file parameter names and their values are identical to the names and values shown in the GUI. Table 4-1 shows the XCO file parameters and values and summarizes t...

Ethernet AVB Endpoint User Guide www.xilinx.com 39 UG492 July 23, 2010 Chapter 5 Core Architecture As described in Chapter 4, “Generating the Core” , the core can be generated in one of two formats, the functionality of which is described in this chapter: • “Standard CORE Generator Format” (provided...

40 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Architecture Standard CORE Generator Format Figure 5-1 illustrates the functional blocks of the Ethernet AVB Endpoint core when it is generated in standard CORE Generator format. As illustrated, this is intended t...

Ethernet AVB Endpoint User Guide www.xilinx.com 41 UG492 July 23, 2010 EDK pcore Format EDK pcore Format Figure 5-2 illustrates the functional blocks of the Ethernet AVB Endpoint core when it is generated in EDK pcore format. As illustrated, this is intended to be connected to the XPS LocalLink Tri-...

42 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Architecture Functional Block Description The following functional blocks described in the following sections are illustrated in Figure 5-1 and Figure 5-2 . PLB Interface The core provides a PLB version 4.6 interf...

Ethernet AVB Endpoint User Guide www.xilinx.com 43 UG492 July 23, 2010 Functional Block Description Tx Arbiter Data for transmission over an AVB network can be obtained from three types of sources: 1. AV Traffic. For transmission from the AV Traffic I/F of the core. 2. Precise Timing Protocol (PTP) ...

44 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Architecture Precise Timing Protocol Blocks The various hardware Precise Timing Protocol (PTP) blocks within the core provide the dedicated hardware to implement the IEEE P802.1AS specification. However, the full ...

Ethernet AVB Endpoint User Guide www.xilinx.com 45 UG492 July 23, 2010 Functional Block Description RTC A significant component of the PTP network wide timing synchronization mechanism is the Real Time Counter (RTC), which provides the common time of the network. Every device on the network will mai...

46 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Architecture Software Drivers Software Drivers are delivered with the Ethernet AVB Endpoint core. These drivers provide functions which utilize the dedicated hardware within the core for the PTP IEEE P802.1AS spec...

Ethernet AVB Endpoint User Guide www.xilinx.com 47 UG492 July 23, 2010 Core Interfaces Core Interfaces All ports of the core are internal connections in FPGA fabric. All clock signals are inputs and no clock resources are used by the core. This enables clock circuitry to be implemented externally to...

48 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Architecture Legacy Traffic Interface Legacy Traffic Transmitter Path Signals Table 5-2 defines the core client-side legacy traffic transmitter signals. These signals are used to transmit data from the legacy clie...

Ethernet AVB Endpoint User Guide www.xilinx.com 49 UG492 July 23, 2010 Core Interfaces AV Traffic Interface AV Traffic Transmitter Path Signals Table 5-4 defines the core client-side AV traffic transmitter signals, used to transmit data from the AV client logic into the core. All signals are synchro...

50 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Architecture AV Traffic R eceiver Path Signals Table 5-5 defines the core client side AV traffic receiver signals, used by the core to transfer data to the AV client. All signals are synchronous to the MAC receive...

Ethernet AVB Endpoint User Guide www.xilinx.com 51 UG492 July 23, 2010 Core Interfaces MAC Receiver Interface These signals connect directly to the identically named Tri-Mode Ethernet MAC signals and are synchronous to rx_clk MAC Management Interface This interface is only present when the core is g...

Ethernet AVB Endpoint User Guide www.xilinx.com 53 UG492 July 23, 2010 Core Interfaces PLB Interface Table 5-9 defines the signals on the PLB bus. For detailed information, see the IBM PLB specification. Shaded rows represent signals not used by this core; inputs are ignored and outputs are tied to ...

Ethernet AVB Endpoint User Guide www.xilinx.com 55 UG492 July 23, 2010 Core Interfaces Interrupt Signals Table 5-10 defines the interrupt signals asserted by the core. All interrupts are active high and are automatically asserted. All interrupts, required by the “Software Drivers” delivered with the...

56 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Architecture PTP Signals Table 5-11 defines the signals which are output from the core by the “Precise Timing Protocol Blocks.” These signals are provided for reference only and may be used by an application. For ...

Ethernet AVB Endpoint User Guide www.xilinx.com 57 UG492 July 23, 2010 Chapter 6 Ethernet AVB Endpoint Transmission As illustrated in Figure 5-1 , data for transmission over an AVB network can be obtained from three types of sources: 1. AV Traffic. For transmission from the “Tx AV Traffic I/F” of th...

58 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 6: Ethernet AVB Endpoint Transmission Error Free Legacy Frame Transmission Figure 6-1 illustrates the timing of a normal frame transfer. When the legacy client initiates a frame transmission, it places the first column of...

Ethernet AVB Endpoint User Guide www.xilinx.com 59 UG492 July 23, 2010 Tx AV Traffic I/F Errored Legacy Frame Transmission The legacy_tx_underrun is provided to give full backwards compatibility between the Legacy Traffic I/F and the client interface of the Tri-Mode Ethernet MAC. The legacy_tx_under...

60 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 6: Ethernet AVB Endpoint Transmission Figure 6-3 illustrates the timing of a normal frame transfer. When the AV client initiates a frame transmission, it places the first column of data onto the av_tx_data[7:0] port and a...

Ethernet AVB Endpoint User Guide www.xilinx.com 61 UG492 July 23, 2010 Tx Arbiter Tx Arbiter Overview As illustrated in Figure 5-1 , data for transmission over an AVB network can be obtained from three types of sources: 1. AV Traffic. For transmission from the AV Traffic I/F of the core. 2. Precise ...

62 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 6: Ethernet AVB Endpoint Transmission Figure 6-4 illustrates the key features of the credit based algorithm, which are: • The Tx Arbiter will schedule queued transmission from the “Tx AV Traffic I/F” if the algorithm is i...

Ethernet AVB Endpoint User Guide www.xilinx.com 63 UG492 July 23, 2010 Tx Arbiter • During AV traffic transmission, credit is removed at a rate defined by the sendSlope. • The hiLimit and loLimit settings impose a fixed range on the possible values of credit. If the available credit hits one of thes...

64 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 6: Ethernet AVB Endpoint Transmission hiLimit The general equation is: hiLimitValue = 2000 x idleSlopeValue In this general equation, the value of 2000 is obtained from the maximum number of bytes which may be present in ...

Ethernet AVB Endpoint User Guide www.xilinx.com 65 UG492 July 23, 2010 Chapter 7 Ethernet AVB Endpoint Reception Rx Splitter The input to the Rx splitter (see Figure 5-1 ) is connected directly to the client Receive (Rx) interface of the connected Ethernet MAC. Received data from an AVB network can ...

66 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 7: Ethernet AVB Endpoint Reception Error Free Legacy Frame Reception Figure 7-1 illustrates the timing of a normal inbound error free frame transfer that has been accepted by the “Legacy MAC Header Filters” The legacy cli...

Ethernet AVB Endpoint User Guide www.xilinx.com 67 UG492 July 23, 2010 Rx Legacy Traffic I/F Errored Legacy Frame Reception As illustrated in Figure 7-2 , reception of any frame in which the legacy_rx_frame_bad is asserted (in place of legacy_rx_frame_good) indicates that this frame must be discarde...

68 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 7: Ethernet AVB Endpoint Reception Figure 7-3 illustrates Legacy frame reception for an error free frame in which at least one of the eight individual MAC Header Filters obtained a match (filter number 3 is illustrated as...

Ethernet AVB Endpoint User Guide www.xilinx.com 69 UG492 July 23, 2010 Rx Legacy Traffic I/F MAC Header Filter Configuration The MAC Header Filters can be enabled or disabled by using the “Rx Filtering Control Register.” This contains a Promiscuous Mode bit, which: • when enabled allows all frames t...

70 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 7: Ethernet AVB Endpoint Reception Single MAC Header Filter Usage Examples Full Destination Address (DA) Match The example illustrated in Figure 7-4 shows a single MAC Header Filter (one of the eight provided) configured ...

Ethernet AVB Endpoint User Guide www.xilinx.com 71 UG492 July 23, 2010 Rx Legacy Traffic I/F Partial Destination Address (DA) Match The example illustrated in Figure 7-5 shows a single MAC Header Filter (one of the eight provided) configured to filter on a partial Destination Address. In order for t...

72 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 7: Ethernet AVB Endpoint Reception VLAN Priority Match The example illustrated in Figure 7-6 shows a single MAC Header Filter (one of the eight provided) configured to filter on frames containing a VLAN tag with a VLAN Pr...

Ethernet AVB Endpoint User Guide www.xilinx.com 73 UG492 July 23, 2010 Rx AV Traffic I/F Rx AV Traffic I/F The signals forming the Rx AV Traffic I/F are defined in Table 5-5 . all signals are synchronous to the Tri-Mode Ethernet MAC receiver clock, rx_clk , which must always be qualified by the corr...

74 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 7: Ethernet AVB Endpoint Reception Errored AV Traffic Reception As illustrated in Figure 7-8 , reception of any frame in which the av_rx_frame_bad is asserted (in place of av_rx_frame_good) indicates that this frame must ...

Ethernet AVB Endpoint User Guide www.xilinx.com 75 UG492 July 23, 2010 Chapter 8 Real Time Clock and Time Stamping This chapter considers two of the logical components that are partially responsible for the AVB timing synchronization protocol. • “Real Time Clock” • “Time Stamping Logic” These are bo...

Ethernet AVB Endpoint User Guide www.xilinx.com 77 UG492 July 23, 2010 Real Time Clock RTC Implementation Increment of Nanoseconds Field Figure 8-2 illustrates the implementation used to create the RTC nanoseconds field. This is performed by the use of an implementation specific 20-bit sub-nanosecon...

78 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 8: Real Time Clock and Time Stamping There are two stages to the implementation: (Step 1) Controlled Frequency RTC The RTC Increment Value illustrated in Figure 8-2 is set directly from the “RTC Increment Value Control Re...

Ethernet AVB Endpoint User Guide www.xilinx.com 79 UG492 July 23, 2010 Time Stamping Logic Clock Outputs Based on the Synchronized RTC Nanoseconds Field The clk8k (8 kHz clock) output, derived from the Synchronized RTC, is provided as an output from the core. The synchronized RTC counter, unlike the...

80 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 8: Real Time Clock and Time Stamping Time Stamp Sampling Position of MAC Frames A time stamp value should be sampled at the beginning of the first symbol following the Start of Frame Delimiter (SFD) of the Ethernet MAC fr...

Ethernet AVB Endpoint User Guide www.xilinx.com 81 UG492 July 23, 2010 IEEE1722 Real Time Clock Format Because the Xilinx Tri-Mode Ethernet MACs have a known fixed latency, the time stamps taken can easily be translated into the equivalent GMII position to comply with the standard. This is performed...

Ethernet AVB Endpoint User Guide www.xilinx.com 83 UG492 July 23, 2010 Chapter 9 Precise Timing Protocol Packet Buffers This chapter considers two of the logical components which are partly responsible for the AVB timing synchronization protocol. • “Tx PTP Packet Buffer” • “Rx PTP Packet Buffer” The...

84 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 9: Precise Timing Protocol Packet Buffers Despite the logic and formatting of each individual PTP buffer being identical, the block RAM is pre-initialized at device configuration to hold template copies of each of the PTP...

Ethernet AVB Endpoint User Guide www.xilinx.com 85 UG492 July 23, 2010 Rx PTP Packet Buffer Rx PTP Packet Buffer The Rx PTP packet buffer is illustrated in Figure 9-2 . This provides working memory to hold each received PTP frame. The software drivers, via the PLB configuration bus, can then read an...

Ethernet AVB Endpoint User Guide www.xilinx.com 87 UG492 July 23, 2010 Chapter 10 Configuration and Status This chapter provides general guidelines for configuring and monitoring the Ethernet AVB Endpoint core, including an introduction to the PLB configuration bus and a description of the core mana...

Ethernet AVB Endpoint User Guide www.xilinx.com 89 UG492 July 23, 2010 Processor Local Bus Interface Single Write Transaction Figure 10-2 illustrates a single write data transfer on the PLB. Note the following: • Wait states can be added to the Address cycle by asserting Sl_wait and delaying Sl_addr...

90 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Status PLB Address Map and Register Definitions Figure 10-3 displays an overview of the Address Space occupied by the Ethernet AVB Endpoint core on the PLB. Common across all addressable space, each ...

Ethernet AVB Endpoint User Guide www.xilinx.com 91 UG492 July 23, 2010 PLB Address Map and Register Definitions The entire address space is now described in two sections: • “Ethernet AVB Endpoint Address Space” • “Tri-Mode Ethernet MAC Address Space” (which can be addressed through the Ethernet AVB ...

92 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Status Ethernet AVB Endpoint Address Space Rx PTP Packet Buffer Address Space The Address space of the “Rx PTP Packet Buffer” is 4k bytes, from PLB_base_address to (PLB_base_address + 0x0FFF). This r...

Ethernet AVB Endpoint User Guide www.xilinx.com 93 UG492 July 23, 2010 PLB Address Map and Register Definitions Rx PTP Packet Control Register Table 10-2 defines the associated control register of the “Rx PTP Packet Buffer,” used by the “Software Drivers” to monitor the position of the most recently...

94 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Status Tx Arbiter Send Slope Control Register The sendSlope variable is defined in IEEE P802.1 Qav to be the rate of change of credit, in bits per second, when the value of credit is decreasing (duri...

Ethernet AVB Endpoint User Guide www.xilinx.com 95 UG492 July 23, 2010 PLB Address Map and Register Definitions This register and the registers defined in Table 10-6 and in Table 10-8 are linked. These three offset values will be loaded into the RTC counter logic simultaneously following a write to ...

96 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Status This register and the registers defined in Table 10-11 and in Table 10-12 are linked. When this nanoseconds value register is read, the entire RTC (including the seconds field) is sampled. Tab...

Ethernet AVB Endpoint User Guide www.xilinx.com 97 UG492 July 23, 2010 PLB Address Map and Register Definitions Phase Adjustment Register Table 10-14 describes the Phase Adjustment Register, which has units of nanoseconds. This value is used to correct the 8k clock generation circuit when a new nano...

98 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Status MAC Header Filter Configuration When the core is generated in “EDK pcore Format” , the “Legacy MAC Header Filters” are not included since the xps_ll_temac can optionally contain its own Addres...

100 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Status Tri-Mode Ethernet MAC Address Space When the core is generated in “EDK pcore Format” for import into EDK and connection to the xps_ll_temac, the address space defined in this section is not i...

Ethernet AVB Endpoint User Guide www.xilinx.com 101 UG492 July 23, 2010 PLB Address Map and Register Definitions MAC MDIO Registers The Tri-Mode Ethernet MAC has MDIO master capability. To access an MDIO register via the Ethernet MAC, construct the address as follows: MDIO register address = PLB_bas...

Ethernet AVB Endpoint User Guide www.xilinx.com 103 UG492 July 23, 2010 Chapter 11 Constraining the Core This chapter defines the Ethernet AVB Endpoint core constraints. An example user constraints file (UCF) is provided for the core and the HDL example design. Required Constraints Device, Package, ...

104 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 11: Constraining the Core PERIOD Constraints for Clock Nets PLB_clk The clock provided to PLB_clk must be constrained to the appropriate frequency. Note the frequency range of the embedded processor to which this bus is ...

Ethernet AVB Endpoint User Guide www.xilinx.com 105 UG492 July 23, 2010 Required Constraints rtc_clk The RTC can be incremented from any available clock frequency that is greater than the AVB standards defined minimum of 25 MHz. However, the faster the frequency of the clock, the smaller will be the...

Ethernet AVB Endpoint User Guide www.xilinx.com 111 UG492 July 23, 2010 Chapter 12 System Integration As described in Chapter 4, “Generating the Core” and Chapter 5, “Core Architecture” , the core can be generated in one of two formats: • “Standard CORE Generator Format” This option will deliver the...

112 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integration LogiCORE IP Tri-Mode Ethernet MAC (Soft Core) Tri-Mode Ethernet MAC Core Generation When generating the Tri-Mode Ethernet MAC (TEMAC) core in the CORE Generator software, be sure that the following...

Ethernet AVB Endpoint User Guide www.xilinx.com 113 UG492 July 23, 2010 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Connections Without Ethernet Statistics Figure 12-1 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri- Mode Ethernet MAC (TEMAC) core when not usin...

Ethernet AVB Endpoint User Guide www.xilinx.com 115 UG492 July 23, 2010 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Connections Including Ethernet Statistics Figure 12-2 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri- Mode Ethernet MAC (TEMAC) core when using ...

116 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integration LogiCORE IP Embedded Tri-Mode Ethernet MACs Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper Generation When generating the Virtex-5 FPGA Embedded Ethernet MAC Wrapper (EMAC) in the CORE Genera...

Ethernet AVB Endpoint User Guide www.xilinx.com 117 UG492 July 23, 2010 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Connections Without Ethernet Statistics Figure 12-3 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri- Mode Ethernet MAC (EMAC) core when not using...

118 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integration Because the EMAC core can often be used in different clocking modes, note the following: • The Ethernet transmitter client clock domain must always be connected to the tx_clk input of the Ethernet ...

Ethernet AVB Endpoint User Guide www.xilinx.com 119 UG492 July 23, 2010 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Figure 12-4 illustrates the connection of the Ethernet AVB Endpoint core to the EMAC when using the Ethernet Statistics core. This shares much in common with Figure 12-2 ; howe...

Ethernet AVB Endpoint User Guide www.xilinx.com 121 UG492 July 23, 2010 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Figure 12-5 can be implemented using the Xilinx tool set using two methods: • “Using an EDK Project Top Level” • “Using an ISE Software Top-Level Project” Using an EDK Project ...

122 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integration In this example, the instance of the Ethernet AVB Endpoint core should be assigned a base address in the Microprocessor Hardware Specification (.mhs) file, to match that of the Ethernet AVB Endpoin...

124 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integration Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC The Ethernet AVB Endpoint core should be generated in the “EDK pcore Format” when connecting to the XPS LocalLink Tri-Mode Ethernet MAC core (xp...

126 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integration Figure 12-8 illustrates the connection of the core to an embedded processor subsystem (MicroBlaze™ processor is illustrated). Observe that: • The PLB can be shared across all peripherals as illustr...

Ethernet AVB Endpoint User Guide www.xilinx.com 127 UG492 July 23, 2010 Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC MHS File Syntax The following code extracts are taken from an XPS project which connected the Ethernet AVB Endpoint core to an instance of the xps_ll_temac. This design target...

Ethernet AVB Endpoint User Guide www.xilinx.com 131 UG492 July 23, 2010 Chapter 13 Software Drivers Software drivers delivered with the Ethernet AVB Endpoint core provide the following functions, which utilize the dedicated hardware within the core for the Precise Timing Protocol (PTP) IEEE P802.1AS...

132 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 13: Software Drivers Clock Slave If the core is acting as a clock slave, the local RTC is closely matched to the value and frequency of the network clock master. This is achieved, in part, by receiving the PTP Sync and F...

Ethernet AVB Endpoint User Guide www.xilinx.com 133 UG492 July 23, 2010 Software System Integration For example, in the user software, the AVB drivers can be instanced as follows: /* Allocate an instance of the XAvb device driver */ static XAvb Avb; int Status; XAvb_Config *AvbConfigPtr; . /* Initia...

134 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 13: Software Drivers Core Initialization When Using a LogiCORE IP Tri-Mode Ethernet MAC Note: When connecting to the XPS LocalLink Tri-Mode Ethernet MAC (xps_ll_temac), available in EDK, the MAC is delivered with its own...

Ethernet AVB Endpoint User Guide www.xilinx.com 135 UG492 July 23, 2010 Software System Integration You should also update the following #define if there is a known asymmetry in the propagation delay on the link. This #define models the per-port global variable “delayAsymmetry” as defined in IEEE P8...

136 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 13: Software Drivers * This function is the handler which will be called if the PTP drivers * identify a possible discontinuity in GrandMaster time. * This handler provides an example of how to handle this situation - * ...

Ethernet AVB Endpoint User Guide www.xilinx.com 137 UG492 July 23, 2010 Chapter 14 Quick Start Example Design The quick start steps provided in this chapter let you quickly generate an Ethernet AVB Endpoint core, run the design through implementation with the Xilinx tools, and simulate the design us...

140 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 14: Quick Start Example Design X-Ref Target - Figure 14-2 7. Enter a core instance name in the Component Name field. 8. Maintain the default options on GUI page 1 so that Standard CORE Generator format is selected. 9. Cl...

Ethernet AVB Endpoint User Guide www.xilinx.com 141 UG492 July 23, 2010 Implementing the Example Design Implementing the Example Design After the core is generated, the netlists and example design can be processed by the Xilinx implementation tools. The generated output files include several scripts...

142 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 14: Quick Start Example Design Timing Simulation This section contains instructions for running a timing simulation of the Ethernet AVB Endpoint core using either VHDL or Verilog. A timing simulation model is generated w...

144 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Standard Format) <component_name>/drivers/v2_04_a Files for compiling the low-level drivers provided with the core drivers/avb_v2_04_a/data Data files for automatic integration into Xil...

Ethernet AVB Endpoint User Guide www.xilinx.com 145 UG492 July 23, 2010 Directory and File Contents <project directory>/<component name> The <component name> directory contains the release notes file provided with the core, which may include last-minute changes and updates. <com...

146 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Standard Format) <component name>/implement The implement directory contains the core implementation script files. rx_frame_checker.v[hd] An HDL file which is capable of receiving Ether...

Ethernet AVB Endpoint User Guide www.xilinx.com 147 UG492 July 23, 2010 Directory and File Contents implement/results The results directory is created by the implement script, after which the implement script results are placed in the results directory. <component name>/simulation The simulati...

148 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Standard Format) simulation/timing The timing directory contains timing simulation scripts provided with the core. wave_ncsim.sv IES macro file that opens a wave window and adds signals of in...

Ethernet AVB Endpoint User Guide www.xilinx.com 149 UG492 July 23, 2010 Directory and File Contents <component_name>/drivers/v2_04_a A directory containing the software device drivers for the Ethernet AVB Endpoint core and associated supporting files. drivers/avb_v2_04_a/data The driver data d...

Ethernet AVB Endpoint User Guide www.xilinx.com 151 UG492 July 23, 2010 Implementation Scripts Implementation Scripts The implementation script is either a shell script or batch file that processes the example design through the Xilinx tool flow and is one of the following locations: Linux <proje...

152 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Standard Format) Timing Simulation The test script is a ModelSim, IES, or VCS macro that automates the simulation of the test bench and is in the following location: <project_dir>/<c...

Ethernet AVB Endpoint User Guide www.xilinx.com 153 UG492 July 23, 2010 Example Design Top-Level Example Design HDL The following files describe the top-level example design for the Ethernet AVB Endpoint core. VHDL <project_dir> / <component_name> /example_design/ <component_name>_...

154 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Standard Format) The data field of the frame is designed to create a simple 8-bit binary counter that continues seamlessly across consecutive Ethernet frames. The Ethernet Frame Stimulus bloc...

Ethernet AVB Endpoint User Guide www.xilinx.com 155 UG492 July 23, 2010 Example Design PLB Module The following files describe the logic for the PLB module. VHDL <project_dir> / <component_name> /example_design/ plb_client_logic.vhd Verilog <project_dir> / <component_name> /e...

156 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Standard Format) Demonstration Test Bench Figure 15-2 illustrates the Ethernet AVB Endpoint demonstration test bench, a simple VHDL or Verilog program for exercising the example design and th...

Ethernet AVB Endpoint User Guide www.xilinx.com 157 UG492 July 23, 2010 Example Design Customizing the Test Bench Simulation Run Time The default simulation run time is set to only 40 microseconds, which can be easily extended by editing the simulation_run_time constant, set near the top of the demo...

158 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Standard Format) Viewing the Simulation Wave Form The Simulation Scripts for the selected simulator automatically selects signals of interest from within the DUT and adds them to the simulato...

Ethernet AVB Endpoint User Guide www.xilinx.com 161 UG492 July 23, 2010 Directory and File Contents <component name>/doc The doc directory contains the PDF documentation provided with the core. <component name>/MyProcessorIPLib This is the route directory which should be imported into th...

162 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 16: Detailed Example Design (EDK format) pcores/eth_avb_endpoint_v2_04_a/hdl/vhdl Contains a VHDL wrapper file for the core netlist to enable integration into Platform Studio. pcores/eth_avb_endpoint_v2_04_a/netlist The ...

164 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010 Chapter 16: Detailed Example Design (EDK format) drivers/avb_v2_04_a/src The driver source (src) directory contains the low-level driver source C files. Table 16-9: Driver Source Directory Name Description <project_dir>/&l...

Ethernet AVB Endpoint User Guide www.xilinx.com 167 UG492 July 23, 2010 Appendix A RTC Time Stamp Accuracy Time Stamp Accuracy The accuracy of the time stamps, taken by sampling the “Real Time Clock” (RTC) whenever PTP frames are transmitted or received, is essential to the Precise Timing Protocol a...

Ethernet AVB Endpoint User Guide www.xilinx.com 169 UG492 July 23, 2010 Time Stamp Accuracy RTC Sampling Error It has to be assumed that the RTC reference clock is of a different frequency to the MAC transmitted and receiver clocks. Therefore, the RTC sampling logic has to be asynchronous. There are...

Ethernet AVB Endpoint User Guide www.xilinx.com 171 UG492 July 23, 2010 Time Stamp Accuracy Accuracy Resulting from the Combined Errors The section “RTC Real Time Instantaneous Error” describes how a maximum error of one RTC reference clock period can result as a consequence of the RTC itself. The s...