Xilinx PCI32 - Manuals - manualsarea.com

Page 2 - Fact Table Notes; Core Implementation

PCI32 Interface v3.0 2 www.xilinx.com DS206 August 31, 2005 Product Specification v3.0.151 Fact Table Notes 1. Resource utilization depends on configuration of the interface and user design. Unused resources are trimmed by the Xilinx technology mapper. The utilization figures reported in this table ...

Page 3 - Notes; Applications; • Hot swap CompactPCI boards; General Description; Spartan

PCI32 Interface v3.0 DS206 August 31, 2005 www.xilinx.com 3 Product Specification v3.0.151 Notes 1. Spartan-3 and Spartan-3E solution pending production speed files.2. For additional Part/Package combinations, see the UCF Generator in the PCI Lounge.3. XC2V1000 is supported over Military Temp. range...

Page 4 - Functional Description

PCI32 Interface v3.0 4 www.xilinx.com DS206 August 31, 2005 Product Specification v3.0.151 Other FPGA resources that can be used in conjunction with the core to enable efficient implementationof a PCI system include: • Block SelectRAM™ memory. Blocks of on-chip ultra-fast RAM with synchronous write ...

Page 5 - Figure 1; PCI I/O Interface Block; Table 2; Parity Generator/Checker; PCI Local Bus Specification

PCI32 Interface v3.0 DS206 August 31, 2005 www.xilinx.com 5 Product Specification v3.0.151 Figure 1 illustrates a user application and the PCI Interface partitioned into five major blocks. PCI I/O Interface Block The I/O interface block handles the physical connection to the PCI bus including all si...

Page 6 - Target State Machine; Interface Configuration; Device and vendor ID; Burst Transfer; Table 3

PCI32 Interface v3.0 6 www.xilinx.com DS206 August 31, 2005 Product Specification v3.0.151 Target State Machine This block controls the PCI interface target functions. The states implemented are a subset of thosedefined in Appendix B of the PCI Local Bus Specification . The target control logic uses...

Page 8 - Timing Specifications; Table 4; Command

PCI32 Interface v3.0 8 www.xilinx.com DS206 August 31, 2005 Product Specification v3.0.151 Timing Specifications The maximum speed at which your user design is capable of running can be affected by the size andquality of the design. The following tables show the key timing parameters for the PCI Int...

Page 9 - Timing Parameters, 66 MHz Implementations; Symbol; Timing Parameters, 33 MHz Implementations

PCI32 Interface v3.0 DS206 August 31, 2005 www.xilinx.com 9 Product Specification v3.0.151 Table 4: Timing Parameters, 66 MHz Implementations Symbol Parameter Min Max T cyc CLK Cycle Time 15 1 30 T high CLK High Time 6 - T low CLK Low Time 6 - T val CLK to Signal Valid Delay(bussed signals) 2 2 6 2 ...

Page 10 - Ordering Information; Build; IP Center; Part Numbers; - Access to the v3.0 PCI32 33 MHz Spartan and 66 MHz Virtex Families

PCI32 Interface v3.0 10 www.xilinx.com DS206 August 31, 2005 Product Specification v3.0.151 Ordering Information Build v3.0.150 of the PCI core, with support added for Spartan-3E, is for available for download from the Xilinx IP Center and can also be accessed through the Xilinx CORE Generator syste...

Page 11 - Revision History; The following table shows the revision history for this document.; Date; Style updates

PCI32 Interface v3.0 DS206 August 31, 2005 www.xilinx.com 11 Product Specification v3.0.151 Revision History The following table shows the revision history for this document. Date Version Revision 07/30/02 1.2 Style updates 12/18/02 1.3 Updated to build v3.0.103; v5.Ii, 1st feature: 32-bit was 64/32...