Xilinx ML561 - Manuals

Virtex-5 FPGA ML561 User Guide www.xilinx.com 5 UG199 (v1.2) April 19, 2008 R Appendix B: Bill of Materials Appendix C: LCD Interface General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Display Hardware D...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 7 UG199 (v1.2) April 19, 2008 R Preface About This Guide This user guide describes the Virtex ® -5 FPGA ML561 Memory Interfaces Development Board. Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on the Xilinx website at...

8 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Preface: About This Guide R - Configurable Logic Blocks (CLBs) - SelectIO™ Resources - SelectIO Logic Resources - Advanced SelectIO Logic Resources • Virtex-5 FPGA RocketIO GTP Transceiver User Guide This guide describes the...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 9 UG199 (v1.2) April 19, 2008 Conventions R Conventions This document uses the following conventions. An example illustrates each convention. Typographical This document uses the following typographical conventions. An example illustrates each convention...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 11 UG199 (v1.2) April 19, 2008 R Chapter 1 Introduction This chapter introduces the Virtex ® -5 FPGA ML561 reference design. It contains the following sections: • “About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit” • “Virtex-5 FPGA ML561 Memory In...

12 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 1: Introduction R Virtex-5 FPGA ML561 Memory Interfaces Development Board A high-level functional block diagram of the Virtex-5 FPGA ML561 Memory Interfaces Development Board is shown in Figure 1-1 . The Virtex-5 FP...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 13 UG199 (v1.2) April 19, 2008 Virtex-5 FPGA ML561 Memory Interfaces Development Board R Figure 1-2 shows the Virtex-5 FPGA ML561 Development Board and indicates the locations of the resident memory devices. Figure 1-2: Virtex-5 FPGA ML561 Development Bo...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 15 UG199 (v1.2) April 19, 2008 R Chapter 2 Getting Started This chapter describes the items needed to configure the Virtex-5 FPGA ML561 Memory Interfaces Development Board. The Virtex-5 FPGA ML561 Development Board is tested at the factory after assembly...

16 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 2: Getting Started R 5. Insert the CompactFlash card included in the kit into socket J27 on the Virtex-5 FPGA ML561 Development Board. To select the startup file, check that SW8 is set to position 0. Applying Power ...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 17 UG199 (v1.2) April 19, 2008 R Chapter 3 Hardware Description This chapter describes the major hardware blocks on the Virtex-5 FPGA ML561 Development Board and provides useful design consideration. It contains the following sections: • “Hardware Overvi...

18 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R FPGA The ML561 uses three Virtex-5 XC5VLX50T-FFG1136 devices, each in a 1136-pin, 35 mm x 35 mm BGA package. Figure 1-1, page 12 shows the memory devices associated with the three FPGAs. Re...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 19 UG199 (v1.2) April 19, 2008 Hardware Overview R Memories Table 3-1 lists the types of memories that the ML561 board supports. When a larger data/strobe ratio is implemented, for example, a x36 QDRII device, the smaller configurations can also be demon...

20 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R DDR2 SDRAM Components The ML561 board contains two 333 MHz Micron MT47H32M16CC-3 (16-bit) DDR2 SDRAM components that provide a 32-bit interface to FPGA #1. Each 16-bit device is packaged in...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 21 UG199 (v1.2) April 19, 2008 Memory Details R Memory Details DDR400 and DDR2 Component Memories The FPGA #1 device on the Virtex-5 FPGA ML561 Development Board is connected to DDR and DDR2 component memories, as shown in Figure 3-3 . Figure 3-3 summari...

22 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R Table 3-3 describes all signals associated with DDR400 Component memories. Table 3-4 describes all signals associated with DDR2 Component memories. For a complete list of FPGA #1 signals an...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 23 UG199 (v1.2) April 19, 2008 Memory Details R DDR2 SDRAM DIMM The FPGA #2 device on the Virtex-5 FPGA ML561 Development Board is connected to DDR2 memories. The DDR2 memory interface includes a 144-bit wide DIMM connection to up to five 240-pin DDR2 DI...

24 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R Table 3-5 describes all the signals associated with DDR2 DIMM component memories. For the Deep DIMM interface to four DIMMs, the individual dedicated control signals are listed at the botto...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 25 UG199 (v1.2) April 19, 2008 Memory Details R QDRII and RLDRAM II Memories Figure 3-5 summarizes the distribution of QDRII and RLDRAM II component interface signals among the different banks of the FPGA #3 device. Figure 3-5: FPGA #3 Banks for QDRII SR...

26 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R Table 3-6 describes all the signals associated with QDRII component memories. XAPP853 : QDR II SRAM Interface for Virtex-5 Devices and its corresponding demo are included on the CD shipped ...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 27 UG199 (v1.2) April 19, 2008 External Interfaces R External Interfaces The external interfaces of the Virtex-5 FPGA ML561 Development Board are described in this section. RS-2 3 2 The ML561 board provides an RS-232 serial interface using a Maxim MAX331...

28 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R 200 MHz LVPECL Clock The 200 MHz LVPECL clock source is an Epson EG-2121CA200M-PCHS oscillator (Y1) with a differential output. The oscillator runs at 200 MHz ± 100 PPM with an operating vo...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 29 UG199 (v1.2) April 19, 2008 External Interfaces R 33 MHz System ACE Controller Oscillator A single-ended 33 MHz Epson SG-8002CA oscillator is provided on the board (Y3) as a clock source for System ACE functionality. GTP Clocks Two SMA connectors are ...

30 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R Seven-Segment Displays One seven-segment display per FPGA (for a total of three) is available for use. The red Stanley-Electric NAR131SB displays are active Low, using seven inputs to displ...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 31 UG199 (v1.2) April 19, 2008 External Interfaces R Power On or Off Slide Switch The power on or off slide switch is a DPST slide switch used to apply input power to the board. While the board contains two such switches, the 5V switch is primarily used ...

32 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R Liquid Crystal Display Connector Previous memory boards such as the ML461 had a DisplaytechQ 64128E-FC-BC-3LP 64x128 LCD panel. This display was removed from the ML561, but the connection i...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 33 UG199 (v1.2) April 19, 2008 Power Regulation R The product specification at http://www.displaytech.com.hk/pdf/graphic/64128e%20series-v10.PDF provides more information. Appendix C, “LCD Interface,” describes the LCD operation in detail. Power Regulati...

34 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R also be supplied from a bench supply using the two banana jacks: J25 (RED) for +5V and J24 (BLACK) for GND. The Rev-A assembly of the Virtex-5 FPGA ML561 Development Board does not support ...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 35 UG199 (v1.2) April 19, 2008 Power Regulation R The FPGA can drive VMARGIN_DN_xxxx_N and VMARGIN_UP_xxxx_N signals, where xxxx indicates one of the six main power regulators: SSTL2, HSTL, SSTL18, VCC1V0, VCC2V5, and VCC3V3. If both voltage-margining in...

36 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R Table 3-18 summarizes the inhibit headers. Board Design Considerations UG086 , Memory Interface Generator (MIG) User Guide includes PCB implementation rules and guidelines to be followed fo...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 37 UG199 (v1.2) April 19, 2008 Board Design Considerations R For Write data and terminations at the memory, if the trace length from the receiver pin to the termination resistor can be guaranteed to be within 0.3 inches, then the fly-by termination schem...

38 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 3: Hardware Description R Table 3-19 shows the details of the dielectric material and construction for each layer and the controlled impedance values for the signal layers. Table 3-19: ML561 Revision A PCB Controlle...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 39 UG199 (v1.2) April 19, 2008 R Chapter 4 Electrical Requirements This chapter provides the electrical requirements for the Virtex-5 FPGA ML561 Development Board. It contains the following sections: • “Power Consumption” • “FPGA Internal Power Budget” P...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 41 UG199 (v1.2) April 19, 2008 Power Consumption R Power Modules Capacity V CCINT Power Plane (1.0V) 1 1.00 15000 15.0 TI PTH05010 15A Module Data Sheet HSTL FPGA Power Plane (1.8V) 1 1.80 15000 27.0 HSTL Memory Power Plane (1.8V) 1 1.80 6000 10.8 TI PTH...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 43 UG199 (v1.2) April 19, 2008 Power Consumption R current can support a voltage swing of up to (16 mA * 50 Ω ) = 800 mV, which is sufficient to meet the output voltage specifications for SSTL18, SSTL2, and HSTL18 I/O standards. Table 4-3 separates the p...

46 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 4: Electrical Requirements R FPGA Internal Power Budget Table 4-4 summarizes power consumption estimates by each of the three XC5VLX50T-FFG1136 FPGAs on the Virtex-5 FPGA ML561 Development Board. This estimate deriv...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 47 UG199 (v1.2) April 19, 2008 R Chapter 5 Signal Integrity Recommendations Termination and Transmission Line Summaries The following are common recommendations for the signal termination scheme to all external memories implemented on the Virtex-5 FPGA M...

48 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 5: Signal Integrity Recommendations R Table 5-1: DDR400 SDRAM Component Terminations Signal FPGA Driver Termination at FPGA Termination at Memory Data (DQ) SSTL2_II_DCI No termination 50 Ω pull-up to 1.3V Data Strob...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 51 UG199 (v1.2) April 19, 2008 R Chapter 6 Configuration This chapter provides a brief description of the FPGA configuration methods used on the Virtex-5 FPGA ML561 Development Board. This chapter contains the following sections: • “Configuration Modes” ...

52 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 6: Configuration R JTAG Chain Four devices (the System ACE chip and three XC5VLX50T-FFG1136 FPGAs) are connected via a JTAG chain on the Virtex-5 FPGA ML561 Development Board. The order of the four devices in the JT...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 53 UG199 (v1.2) April 19, 2008 System ACE Interface R Table 6-2 shows the System ACE interface signal names, descriptions, and pin assignments. Table 6-2: System ACE Interface Signal Descriptions System ACE Pin Number Signal Name 70 SYSACE_MPA0 69 SYSACE...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 55 UG199 (v1.2) April 19, 2008 R Chapter 7 ML561 Hardware-Simulation Correlation This chapter contains the following sections: • “Introduction” • “Test Setup” • “Signal Integrity Correlation Results” • “Summary and Recommendations” • “How to Generate a U...

56 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Hardware-Simulation Correlation R illustrated here for these signals can be easily adopted to perform SI analysis for any other memory interface signal on the ML561 board. This chapter presents the SI resul...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 57 UG199 (v1.2) April 19, 2008 Test Setup R strobe, a random value can be applied to data bits from one cycle to another. A 63-bit PRBS6 (1) (PRBS of order 6) test pattern stimulus is used for this analysis. The value of this PRBS6 string is 63’h03F5_66E...

58 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Hardware-Simulation Correlation R ♦ DDR2 mask (for nominal VDDQ = 1.8V and VREF = 0.9V): - VIH(ac)-min = VREF + 200 mV = 1.1V - VIH(dc)-min = VREF + 125 mV = 1.025V - VIL(ac)-max = VREF – 200 mV = 0.7V - VI...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 59 UG199 (v1.2) April 19, 2008 Signal Integrity Correlation Results R DDR2 Component Write Operation This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from FPGA1 (U7) to the DDR2 memory component (U12) measured at 333 MHz (667 Mb/s), w...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 65 UG199 (v1.2) April 19, 2008 Signal Integrity Correlation Results R DDR2 Component Read Operation This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from the DDR2 memory component (U12) to FPGA1 (U7) measured at 333 MHz (667 Mb/s), wh...

70 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Hardware-Simulation Correlation R DDR2 DIMM Write Operation This subsection shows the test results for the DDR2_DIMM_DQ_BY2_B3 signal from FPGA2 (U5) to the DDR2 DIMM (XP2) measured at 333 MHz (667 Mb/s), w...

76 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Hardware-Simulation Correlation R DDR2 DIMM Read Operation This subsection shows the test results for the DDR2_DIMM_DQ_BY2_B3 signal from the DDR2 DIMM (XP2) to FPGA2 (U5) measured at 333 MHz (667 Mb/s), wh...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 81 UG199 (v1.2) April 19, 2008 Signal Integrity Correlation Results R QDRII Write Operation This subsection shows the test results for the QDR2_D_BY0_B5 signal from FPGA3 (U34) to QDRII memory (U35) measured at 300 MHz (600 Mb/s), where the unit interval...

86 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Hardware-Simulation Correlation R QDRII Read Operation This subsection shows the test results for the QDR2_Q_BY0_B5 signal from QDRII memory (U35) to FPGA3 (U34) measured at 300 MHz (600 Mb/s), where the un...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 91 UG199 (v1.2) April 19, 2008 Summary and Recommendations R Summary and Recommendations The first objective of this exercise is to establish correlation between hardware measurements and the simulation at the probe point. The intention was to validate t...

92 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Hardware-Simulation Correlation R Table 7-16 summarizes the extrapolated SI characteristics of all six test signals. Here are some observations about extrapolated SI characteristics among these test signals...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 93 UG199 (v1.2) April 19, 2008 How to Generate a User-Specific FPGA IBIS Model R How to Generate a User-Specific FPGA IBIS Model The following steps indicate how to generate an IBIS model: 1. Under ISE, open your fully compiled project. 2. Go to the Tcl ...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 95 UG199 (v1.2) April 19, 2008 R Appendix A FPGA Pinouts This appendix provides the pinouts for the three FPGAs on the Virtex-5 FPGA ML561 Development Board. The toolkit CD shipped with every ML561 contains sample UCFs for each memory interface. These UC...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 115 UG199 (v1.2) April 19, 2008 R Appendix B Bill of Materials This appendix lists the bill of materials (BOM) for many of the components used for the assembly of the Virtex-5 FPGA ML561 Development Board, Revision A. Wherever feasible and practical, the...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 119 UG199 (v1.2) April 19, 2008 R Appendix C LCD Interface This appendix describes the LCD interface for the Virtex-5 FPGA ML561 Development Board. General The Virtex-5 FPGA ML561 Development Board has a full graphical LCD panel. This display was chosen ...

120 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Table C-1 summarizes the controller specifications. The on-chip RAM size is 65 x 132 = 8580 bits. Hardware Schematic Diagram Figure C-1 illustrates the schematic for the display. Table C-1: Disp...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 121 UG199 (v1.2) April 19, 2008 Hardware Schematic Diagram R Peripheral Device KS071 3 Figure C-2 is a block diagram of the Samsung KS0713. Figure C-2: KS0713 Block Diagram V/C Circ u it V/R Circ u it V/F Circ u it P a ge Addre ss Circ u it Line Addre ss...

122 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Figure C-3 shows only the signals of interest for the LCD controller. The data sheet from the Samsung web pages provides a complete signal listing. Figure C-4 shows the dimensions for the 64128E...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 123 UG199 (v1.2) April 19, 2008 Hardware Schematic Diagram R Controller – Operation The pixels for the LCD panel are stored in the controller data RAM. This RAM is a 65-row by 132-column array. Each display pixel is represented by a single bit in the RAM...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 125 UG199 (v1.2) April 19, 2008 Hardware Schematic Diagram R When a page is addressed, all the bits representing dots on the LCD panel can be accessed in that page. An array of 8x132 bits is available. The line address dictates what line of the RAM is go...

126 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Controller – Power Supply Circuits Figure C-5 shows the power supply circuits. The power supply is used in the five times boost mode, where VDD is 3.3V and VOUT is 16.5V. VOUT is the operating v...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 127 UG199 (v1.2) April 19, 2008 Hardware Schematic Diagram R The voltage and contrast settings must be configured before the LCD panel is ready for operation. Figure C-6 shows the initialization procedure required to set up the LCD controller. Operation ...

130 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Instruction Set Table C-6 shows the instruction set for the LCD panel. Table C-6: Display Instructions Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read display data 1 1 Read Data 8-bit dat...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 133 UG199 (v1.2) April 19, 2008 Hardware Schematic Diagram R Read/Write Characteristics (6800 Mode) Table C-7 list the read and write timing parameters in 6800 mode. The associated waveforms for these parameters are illustrated in Figure C-7 . Table C-7:...

134 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Design Examples LCD Panel Used in Full Graphics Mode The LCD controller RAM has eight 132-byte pages (in fact, there are nine pages; page 9 is special). Each page is one byte wide. If all the pa...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 135 UG199 (v1.2) April 19, 2008 Hardware Schematic Diagram R LCD Panel Used in Character Mode This design example requires a byte representing a command or data to be displayed as input. • When the Enable signal is Low, nothing happens. The display inter...

136 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Display Data Byte The supplied byte must be a valid ASCII representation of a character as shown in Figure C-9 . The character set is stored in block RAM (used as ROM). The CharacterSet.xls file...

138 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Figure C-11 shows a block diagram of the LCD character generator controller. Character data is latched and then shifted left three positions. This shifted value is the start byte for a counter t...

Virtex-5 FPGA ML561 User Guide www.xilinx.com 139 UG199 (v1.2) April 19, 2008 Hardware Schematic Diagram R Array Connector Numbering Figure C-12 shows the LCD connections for Bank 0. Figure C-12: LCD Connections (Bank 0) B a nk 0 Connector Pin A B C D E F G H I D9 LCD_D0 10 D7 LCD_D4 9 D5 LCD_D5 8 D...