Xilinx ML403 - Manuals - manualsarea.com

Page 2 - Introduction; Figure 1; IIC Primer; Figure 2; ss

Introduction XAPP979 (v1.0) February 26, 2007 www.xilinx.com 2 R Introduction This application note accompanies a reference system built on the ML403 development board. Figure 1 is a block diagram of the reference system. The system uses the embedded PowerPC (PPC) as the microprocessor and the OPB I...

Page 3 - Figure 4; ve

Introduction XAPP979 (v1.0) February 26, 2007 www.xilinx.com 3 R Figure 4 shows the format of the data transfer of two bytes on the IIC bus, beginning with the START (S) condition and ending with the STOP (P) condition, bounded by an idle IIC (F) bus.After a START condition, an eight bit field is tr...

Page 4 - Reference System Specifics; Figure 6; as

Reference System Specifics XAPP979 (v1.0) February 26, 2007 www.xilinx.com 4 R Figure 6 shows the acknowledge bit on the IIC bus. Figure 7 shows bus arbitration of two masters. The IIC bus is a multi-master bus. Masters monitor the IIC bus to determine if the bus is active. The bus is inactive when ...

Page 5 - OPB IIC Registers; Table 2; xFFFFFFFF; Table 2: OPB IIC Registers; Name; Reserved

Reference System Specifics XAPP979 (v1.0) February 26, 2007 www.xilinx.com 5 R ML403 XC4VFX12 Address Map OPB IIC Registers Table 2 provides the register map for the OPB IIC core. Table 3 provides a description of the OPB IIC control register. Table 1: ML403 XC4VSX12 System Address Map Peripheral In...

Page 6 - Table 4; . This bit must be set if arbitration is lost or if a transmit error; Table 4: Status Register Bit Definitions

Reference System Specifics XAPP979 (v1.0) February 26, 2007 www.xilinx.com 6 R Status Register (SR) This register contains the status of the OPB IIC Bus Interface. All bits are cleared upon reset. Table 4 provides a definition of the status register. 27 TXAK Transmit Acknowledge Enable. This bit spe...

Page 7 - Table 5

Reference System Specifics XAPP979 (v1.0) February 26, 2007 www.xilinx.com 7 R Table 5 provides a register description of the Interrupt Status register. 30 AAS Addressed as Slave. When the address on the IIC bus matches theSlave address in the Address Register (ADR), the IIC Bus Interface isbeing ad...

Page 8 - Configuring the OPB IIC Core; Figure 8

Reference System Specifics XAPP979 (v1.0) February 26, 2007 www.xilinx.com 8 R Configuring the OPB IIC Core Figure 8 shows how to specify the values of IIC generics in EDK. To access the dialog box in the figure, double click on the OPB IIC core in the EDK System Assembly View.. Microchip 24LC04 The...

Page 9 - ML403 Board Information; Figure 10: 24LC04 Control Byte Allocation; Figure 11: ML40x Schematic for IIC Connections; CL

ML403 Board Information XAPP979 (v1.0) February 26, 2007 www.xilinx.com 9 R is ‘1010 for read and write operations. The A2, A1 bits are dont cares. The A0 bit is used by themaster device to select which of the two 256-word blocks of memory are accessed. The24LC04 write transactions are either a byte...

Page 10 - The resistors are located on the board as shown in

ML403 Board Information XAPP979 (v1.0) February 26, 2007 www.xilinx.com 10 R The resistors are located on the board as shown in Figure 12 . Figure 12: ML40x Resistors X979_12_022 3 07

Page 11 - The resistor values are dependent on the voltage.

ML403 Board Information XAPP979 (v1.0) February 26, 2007 www.xilinx.com 11 R If additional IIC devices are connected to the bus via the expansion header as shown in Figure 13 , insert additional pull-up resistors on the external signals connected at pins 31 and 32. The resistor values are dependent ...

Page 12 - shows the FPGA pins driving the IIC Bus.; TotalPhase Aardvark Adapter; Figure 14: FPGA IIC Pins

ML403 Board Information XAPP979 (v1.0) February 26, 2007 www.xilinx.com 12 R Figure 14 shows the FPGA pins driving the IIC Bus. TotalPhase Aardvark Adapter In the reference design, the OPB IIC in the XC4VFX12 on the ML403 board interfaces to the IICin the Aardvark Adapter. The Aardvark IIC/SPI Embed...

Page 13 - shows the Aardvark Control Center GUI.

ML403 Board Information XAPP979 (v1.0) February 26, 2007 www.xilinx.com 13 R Figure 15 shows the Aardvark Control Center GUI. Interfacing to the OPB IIC on the ML403 Board to the AardvarkAdapter Figure 16 shows the principle interface blocks when transferring data between the OPB IIC in the XC4VFX12...

Page 14 - Executing the Reference System from EDK; Generate Bitstream to generate a bitstream; Software Projects; src; Projects interfacing to Microchip 24LC04

ML403 Board Information XAPP979 (v1.0) February 26, 2007 www.xilinx.com 14 R 3. Invoke XMD and connect to the MicroBlaze processor by the following command: xmd -opt xapp.opt 4. Download the executable by the following command dow <path>/executable.elf Executing the Reference System from EDK T...

Page 15 - Projects interfacing to Aardvark Adapter; shows the repeated start example.

ML403 Board Information XAPP979 (v1.0) February 26, 2007 www.xilinx.com 15 R low_level_dynamic_eeprom: This project transmits and receives data using the low level (L0)software driver. The OPB IIC is the master and the 24LC04 is configured as the slave. The OPBIIC master writes data into the 24LC04 ...

Page 16 - Running the Applications; shows the structure of the

Running the Applications XAPP979 (v1.0) February 26, 2007 www.xilinx.com 16 R Figure 18 shows the slave example. The message is in transmit.txt, and is the sentence "Lester was here.". The transaction log matches the message. The address is 0x70. Click MasterWrite to generate the transaction...

Page 17 - From XPS, start XMD and enter; rst; shown in

Running the Applications XAPP979 (v1.0) February 26, 2007 www.xilinx.com 17 R Select dynamic_eeprom and right click to build the project. If more than one software projectis used, make the unused software projects inactive. Connect a serial cable to the RS232C port on the ML403 board. Start up a Hyp...

Page 18 - Figure 22: ChipScope Inserter Setup

Using ChipScope with OPB IIC XAPP979 (v1.0) February 26, 2007 www.xilinx.com 18 R UsingChipScope withOPB IIC To facilitate the use of ChipScope to analyze OPB IIC hardware, the iic.cdc file is included in the ml403_ppc_opb_iic/chipscope directory. The iic.cdc is used to insert a ChipScope ILA core i...

Page 19 - intr; Figure 23: Making Net Connections in ChipScope Inserter

Using ChipScope with OPB IIC XAPP979 (v1.0) February 26, 2007 www.xilinx.com 19 R 5. Figure 23 shows the GUI for making net connections. Click Next to move to the Modify Connections window. If there are any red data or trigger signals, correct them. The Filter Pattern can be used to find net(s). As ...

Page 20 - Using ChipScope with OPB IIC; As shown in

Using ChipScope with OPB IIC XAPP979 (v1.0) February 26, 2007 www.xilinx.com 20 R The waveform viewer is more readable when buses rather than discrete signals are displayed.The Reverse Bus Order operation below Add to Bus in the figure can be useful in analyzingChipScope results. 11. Set the trigger...

Page 21 - vcd2wlf; Linux Kernel; Add; To generate the Linux LSP in XPS, enter Software; Figure 25: ChipScope Analyzer Results

Linux Kernel XAPP979 (v1.0) February 26, 2007 www.xilinx.com 21 R 13. ChipScope results are analyzed in the waveform window as shown in Figure 25 . The waveforms may be easier to read if the discrete signals are removed after they are renamed. Toshare the results with remote colleagues, save the res...

Page 22 - Figure 26: BSP Settings

Linux Kernel XAPP979 (v1.0) February 26, 2007 www.xilinx.com 22 R 5. Under OS and Libraries, set the entries as shown in Figure 26 . Verify that the target directory is the same as the directory containing the Linux source. Figure 26: BSP Settings X979_26_012907

Page 23 - make oldconfig; make menuconfig; Figure 27: Connected Peripherals

Linux Kernel XAPP979 (v1.0) February 26, 2007 www.xilinx.com 23 R 6. Click Connect_Periphs and add the OPB_INTC, OPB_SYSACE, OPB_IIC, OPB_SPI,OPB_IIC, and OPB 16550 peripherals, using the instance names shown in Figure 27 . Click OK. 7. Select Software → Generate Libraries and BSPs to generate the L...

Page 24 - Simulation; Open

Simulation XAPP979 (v1.0) February 26, 2007 www.xilinx.com 24 R command from the command prompt: impact -batch etc/download.cmd 12. Invoke XMD. From the ml403_ppc_opb_iic/linux directory, enter the following commands in the XMD window. rst dow arch/ppc/boot/images/zImage.initrd.elf con 13. View the ...

Page 25 - Internal signal names used in the OPB IIC core are provided in; BFM

Simulation XAPP979 (v1.0) February 26, 2007 www.xilinx.com 25 R In most cases, after data is transmitted, the test waits for an interrupt from the OPB IIC. Internal signal names used in the OPB IIC core are provided in Table 6 . Figure 28: OPB IIC Simulation Table 6: Internal Signals in OPB IIC Sign...

Page 26 - The simulation runs for 2000 ns as shown in

Simulation XAPP979 (v1.0) February 26, 2007 www.xilinx.com 26 R The simulation runs for 2000 ns as shown in Figure 29 . There are 3 sections in the simulation, shown in the following figures. Figure 29: Complete Simulation X979_29_022 3 07

Page 27 - In the first test, which is shown in

Simulation XAPP979 (v1.0) February 26, 2007 www.xilinx.com 27 R In the first test, which is shown in Figure 30 , the OPB IIC registers are read to verify the correct reset values. The interrupt registers are written and read. This occurs from 0 - 10 s. Followingthis, an arbitration test is run. IIC_...

Page 28 - Figure 31: Arbitration Lost Test Code

Simulation XAPP979 (v1.0) February 26, 2007 www.xilinx.com 28 R Figure 31 provides the Arbitration Lost test code. This pseudo-code can be tracked in the simulation. Figure 31: Arbitration Lost Test Code wri te AD R_20 0x20 wri te CR_20 40 wri te CR_AA 0x01 wri te AD R_AA AA wri te IER_AA 0x04 wri t...

Page 29 - The second test, shown in

Simulation XAPP979 (v1.0) February 26, 2007 www.xilinx.com 29 R The second test, shown in Figure 32 , runs from 575 s to 790 s ., Ths master, AA, receives 3C and 55 from 20. The following stimuli / results is seen in the opb_iic.wlf file. Figure 32: Simulation with iic_AA as Master X979_ 3 2_022 3 0...

Page 30 - Figure 33: Test code with iic_AA as Master

Simulation XAPP979 (v1.0) February 26, 2007 www.xilinx.com 30 R Figure 33 provides the test code used in the simulation with the OPB IIC with the AA address as the master. Figure 33: Test code with iic_AA as Master wri te CR_20 0x40 -- GC, En wri te AD R_20 0x20 - S et s a ddr e ss as 0x20 wri te CR...

Page 31 - shows the third test shown in

Simulation XAPP979 (v1.0) February 26, 2007 www.xilinx.com 31 R Figure 34 shows the third test shown in opb_iic.wlf , run from 800 - 2000 us. IIC_20 is the master writing to IIC_AA, which is a 10-bit slave. Figure 34: Simulation with iic_AA as Master X979_ 3 4_012907

Page 32 - provides the test code for simulation with IIC_AA as master.

Simulation XAPP979 (v1.0) February 26, 2007 www.xilinx.com 32 R Figure 35 provides the test code for simulation with IIC_AA as master. Figure 35: Test Code for Simulation with iic_20 as Master write DTR_20 0xF2write DTR_20 0xD5read TX_FIFO_OCY 0x01write CR_20 0x0D -- Tx, MS, Enwrite RC_FIFO_PIRQ 0x0...

Page 33 - References; XAPP765 Getting Started with EDK and MontaVista Linux; Initial Xilinx release.

References XAPP979 (v1.0) February 26, 2007 www.xilinx.com 33 R References DS434 OPB IIC Bus Interface (v1.02a) XAPP765 Getting Started with EDK and MontaVista Linux ML40x Embedded Development Platform User Guide UG080 (v2.5) May 24, 2006 ChipScope ILA Tools Tutorial The IIC Bus Specification Versio...