Texas Instruments TMS320C6457 DSP - Manual

Texas Instruments TMS320C6457 DSP

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Table of Contents:

  • Page 3 – Contents
  • Page 8 – Read This First; About This Manual; — TMS320C6000 DSP CPU and Instruction Set Reference Guide.; Trademarks
  • Page 9 – Features
  • Page 10 – Introduction; Encoding is done as shown in; Figure 1. 3GPP and IS2000 Turbo-Encoder Block Diagram; Figure 2
  • Page 11 – Overview; a priori; Figure 2. 3GPP and IS2000 Turbo-Decoder Block Diagram; Figure 3
  • Page 12 – Figure 3. TCP2 Block Diagram; Figure 4
  • Page 13 – Input Data Format; Systematic and Parity Data
  • Page 16 – Interleaver Indexes; Output Decision Data Format; interleaver table; Table 2. Interleaver Data
  • Page 17 – Stopping Test Unit; SNR Threshold Termination
  • Page 18 – Parameter Termination; Maximum Iterations
  • Page 20 – Figure 17. Subframe Equations
  • Page 22 – . The DSP has to split
  • Page 24 – A Priori Data; Output Data Format; A priori data for MAP0 and MAP1 must be organized as described in; Figure 31. A Priori Data
  • Page 25 – Registers; The memory map is listed in; Table 3. TCP2 Registers
  • Page 27 – and described in
  • Page 28 – TCP2 Input Configuration Register 0 (TCPIC0); The TCP2 input configuration register 0 (TCPIC0) is shown in
  • Page 29 – The TCP2 input configuration register 1 (TCPIC1) is shown in
  • Page 30 – TCP2 Input Configuration Register 3 (TCPIC3); The TCP2 input configuration register 3 (TCPIC3) is shown in
  • Page 31 – TCP2 Input Configuration Register 4 (TCPIC4); The TCP2 input configuration register 4 (TCPIC4) is shown in
  • Page 32 – The TCP2 input configuration register 5 (TCPIC5) is shown in; Table 12. CRC Examples
  • Page 33 – TCP2 Input Configuration Register 6 (TCPIC6); The TCP2 input configuration register 6 (TCPIC6) is shown in; CDMA-2000 Tail Symbol Pattern for Code Rate 1/5
  • Page 34 – The TCP2 input configuration register 7 (TCPIC7) is shown in; CDMA-2000 Tail Symbol Pattern for Code Rate 1/4
  • Page 36 – The TCP2 input configuration register 9 (TCPIC9) is shown in
  • Page 39 – The TCP2 input configuration register 12 (TCPIC12) is shown in
  • Page 40 – The TCP2 input configuration register 14 (TCPIC14) is shown in
  • Page 41 – The TCP2 input configuration register 15 (TCPIC15) is shown in; Table 23. Extrinsic Scale Registers
  • Page 42 – The TCP2 output parameter register 0 (TCPOUT0) is shown in
  • Page 43 – The TCP2 output parameter register 2 (TCPOUT2) is shown in; Table 27. TCP2 Execution Register (TCPEXE) Field Descriptions
  • Page 44 – The TCP2 endian register (TCPEND) is shown in
  • Page 45 – The TCP2 error register (TCPERR) is shown in
  • Page 47 – The TCP2 status register (TCPSTAT) is shown in
  • Page 49 – Table 31. TCP2 Emulation Register (TCPEMU) Field Descriptions
  • Page 50 – Data Memory for Systematic; Endianness; This architecture supports both big- and little-endian operation.
  • Page 51 – Figure 61. Data Memory
  • Page 53 – Hard Decision Data
  • Page 54 – TCP_ENDIAN Register for Endianness Manager; Table 32. Hard Decisions in DSP Memory; They have to be swapped as described in
  • Page 55 – Interleaver Data; Table 33. TCP_ENDIAN Programming Register; Table 34. Interleaver Data
  • Page 56 – Table 36. Interleaver Indexes in DSP Memory
  • Page 57 – Extrinsic Data; Table 37. Extrinsic Data
  • Page 59 – Architecture
  • Page 60 – Sub-block and Sliding Window Segmentation; Figure 95. MAP Unit Block Diagram; Alpha prolog portion
  • Page 61 – for the number of sub-blocks and sliding windows.
  • Page 62 – Reliability and Prolog Length Calculation
  • Page 63 – Ǔ w; Added Features; Code Rates; Figure 98. Example R Formula
  • Page 64 – Programming; Table 41. Valid Re-Encode Symbols Used for Comparison
  • Page 65 – EDMA3 Resources; TCP2 Dedicated EDMA3 Resources; The EDMA3 parameters consists of eight words as shown in; Figure 99. EDMA3 Parameters Structure
  • Page 66 – EDMA3 Programming; Input Configuration Parameters Transfer; SPRUGK6
  • Page 67 – Interleaver Indexes Transfer; information on how to setup a dummy Xfer, see the
  • Page 68 – Hard-Decisions Transfer; Access (EDMA3) Controller Reference Guide
  • Page 69 – Output Parameters Transfer; Input Configurations Parameters Programming; decoded and the OUTF bit is cleared.
  • Page 70 – through; To decode the whole frame, follow these steps:
  • Page 71 – ITCCEN = 0 (Intermediate transfer complete chaining is disabled)
  • Page 72 – A Priori Transfer; LINK ADDRESS: See cases 1 and 2 below
  • Page 73 – Extrinsics Transfer
  • Page 74 – Output Parameters; Mode; The various output parameters are described in
  • Page 75 – Debug Mode: Pause After Each Map; = debug mode. Normal initialization and wait in MAP state 0.
  • Page 76 – Errors and Status
  • Page 77 – The TCP2 status register (TCPSTAT) reflects the state of the TCP2.
  • Page 78 – The Active_state indicates active MAP decoder state.
  • Page 79 – IMPORTANT NOTICE
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TMS320C6457 DSP
Turbo-Decoder Coprocessor 2 (TCP2)

User's Guide

Literature Number: SPRUGK1

March 2009

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Summary

Page 3 - Contents

Contents Preface ........................................................................................................................................ 8 1 Features .............................................................................................................................. 9 2 In...

Page 8 - Read This First; About This Manual; — TMS320C6000 DSP CPU and Instruction Set Reference Guide.; Trademarks

Preface SPRUGK1 – March 2009 Read This First About This Manual Channel decoding of high bit-rate data channels found in third-generation (3G) cellular standards requiresdecoding of turbo-encoded data. The turbo-decoder coprocessor (TCP2) in some of the digital signalprocessors (DSPs) of the TMS320C6...

Page 9 - Features

1 Features User's Guide SPRUGK1 – March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 Channel decoding of high bit-rate data channels found in third-generation (3G) cellular standards requiresdecoding of turbo-encoded data. The turbo-decoder coprocessor (TCP2) in some of the digital signalprocessor (...

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