Texas Instruments TMS320C6202 - Manual
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Table of Contents:
- Page 3 – FIXED-POINT DIGITAL SIGNAL PROCESSOR; description; debugger interface for visibility into source code; device characteristics; Table 1. Characteristics of the ’C6202 Processors; ADV
- Page 4 – functional block diagram
- Page 5 – CPU description
- Page 8 – signal groups description; Figure 3. CPU Signals
- Page 9 – Figure 4. Peripheral Signals
- Page 11 – Signal Descriptions
- Page 22 – development support; The; Table 2. TMS320C6xx Development-Support Tools
- Page 23 – Device development evolutionary flow:
- Page 25 – documentation support
- Page 27 – clock PLL; input and output clocks section for input; Figure 6. PLL Block Diagram; power-supply sequencing
- Page 28 – recommended operating conditions
- Page 29 – PARAMETER MEASUREMENT INFORMATION; signal transition levels
- Page 30 – Figure 8. CLKIN Timings; timing requirements for XCLKIN; Figure 9. XCLKIN Timings
- Page 31 – switching characteristics for CLKOUT1; Figure 10. CLKOUT1 Timings; switching characteristics for CLKOUT2; Figure 11. CLKOUT2 Timings
- Page 32 – switching characteristics for XFCLK; Figure 12. XFCLK Timings
- Page 33 – ASYNCHRONOUS MEMORY TIMING
- Page 35 – SYNCHRONOUS-BURST MEMORY TIMING
- Page 36 – Figure 15. SBSRAM Read Timing; Figure 16. SBSRAM Write Timing
- Page 37 – SYNCHRONOUS DRAM TIMING
- Page 39 – Figure 19. SDRAM ACTV Command
- Page 41 – timing requirements for the HOLD/HOLDA cycles
- Page 43 – Figure 24. Reset Timing
- Page 44 – Figure 25. Interrupt Timing
- Page 45 – EXPANSION BUS SYNCHRONOUS FIFO TIMING
- Page 46 – EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED); Figure 27. FIFO Read Timing
- Page 47 – EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING
- Page 48 – EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED); Figure 29. Expansion Bus Asynchronous Peripheral Read Timing
- Page 49 – EXPANSION BUS SYNCHRONOUS HOST PORT TIMING
- Page 50 – EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED); Figure 31. External Host as Bus Master—Read
- Page 51 – Figure 32. External Host as Bus Master—Write
- Page 54 – Figure 35. ’C6202 as Bus Master—BOFF Operation
- Page 55 – EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING; Figure 36. External Device as Asynchronous Master—Read
- Page 56 – EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING (CONTINUED); Figure 37. External Device as Asynchronous Master—Write
- Page 57 – Figure 38. Expansion Bus Arbitration—Internal Arbiter Enabled
- Page 58 – Figure 39. Expansion Bus Arbitration—Internal Arbiter Disabled
- Page 59 – MULTICHANNEL BUFFERED SERIAL PORT TIMING
- Page 61 – MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED); Figure 40. McBSP Timings
- Page 69 – switching characteristics for DMAC outputs; Figure 46. DMAC Timing; timing requirements for timer inputs; Figure 47. Timer Timing
- Page 70 – switching characteristics for power-down outputs
- Page 71 – JTAG TEST-PORT TIMING; switching characteristics for JTAG test port (see Figure 49)
- Page 72 – MECHANICAL DATA; PLASTIC BALL GRID ARRAY
- Page 74 – IMPORTANT NOTICE; Copyright
TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
1
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
D
Highest Performance Fixed-Point Digital
Signal Processor (DSP) TMS320C6202
– 4-ns Instruction Cycle Time
– 250-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 2 000 MIPS
D
VelociTI
Advanced Very Long Instruction
Word (VLIW) ’C6200 CPU Core
– Eight Highly Independent Functional
Units:
– Six ALUs (32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Result)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
D
Instruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 32-Bit Address Range
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
D
3M-Bit On-Chip SRAM
– 2M-Bit Internal Program/Cache
– Two 128K-Byte Blocks Offer Improved
Concurrency
Block 0: 128K Bytes Memory-Mapped
Block 1: 128K Bytes Direct-Mapped
Cache/Memory-Mapped
– 1M-Bit Dual-Access Internal Data
(128K Bytes)
– Two 64K-Byte Blocks Offer Improved
Concurrency
D
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
D
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
D
Flexible Phase-Locked-Loop (PLL) Clock
Generator
D
32-Bit Expansion Bus
– Glueless/Low-Glue Interface to Popular
PCI Bridge Chips
– Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous
Microprocessor Buses
– Master/Slave Functionality
– Glueless Interface to Synchronous FIFOs
and Asynchronous Peripherals
D
Three Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral-Interface (SPI)
Compatible (Motorola
)
D
Two 32-Bit General-Purpose Timers
D
IEEE-1149.1 (JTAG
†
)
Boundary-Scan-Compatible
D
352-Pin BGA Package (GJL Suffix)
D
384-Pin BGA Package (GLS Suffix)
D
0.18-
µ
m/5-Level Metal Process
– CMOS Technology
D
3.3-V I/Os, 1.8-V Internal
ADV
ANCE INFORMA
TION
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright
1999, Texas Instruments Incorporated
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Summary
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description The TMS320C62x DSPs (including the TMS320C6202 device) are the fixed-point DSP family in theTMS320C6000 platform. The TMS320C6202 (’C6202) devi...
TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram EMIF Timers Interrupt Selector McBSPs XB Control DMA Control EMIF Control Expansion Bus (XB) Interface PLL Power Down Boot- Config....
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 CPU description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight32-bit instructions to the eight ...
