Page 3 - Contents
Contents Preface ....................................................................................................................................... 7 1 Introduction ........................................................................................................................ 9 1.1 Pur...
Page 7 - Read This First; About This Manual
Preface SPRU970G – December 2005 – Revised June 2011 Read This First About This Manual This document describes the DDR2 memory controller in the TMS320C6455/C6454 digital signalprocessors (DSPs). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown wit...
Page 9 - Introduction; Purpose of the Peripheral; Figure 1
User ' s Guide SPRU970G – December 2005 – Revised June 2011 C6455/C6454 DDR2 Memory Controller 1 Introduction 1.1 Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79-2B standard compliant DDR2 SDRAMdevices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asy...
Page 10 - Figure 1. Device Block Diagram; Industry Standard(s) Compliance Statement
L1 S1 M1 D1 Data path A Register file A Register file B D2 Data path B S2 M2 L2 L1 data memory controller Cache control Memory protection Interrupt and exception controller Power control Instruction decode 16/32−bit instruction dispatch Instruction fetch SPLOOP buffer C64x+ CPU IDMA Bandwidth manage...
Page 11 - Peripheral Architecture; Section 3; Clock Control; DDR2CLKOUT frequency = (PLL2 input clock frequency; Memory Map; The DDR2 memory controller signals are shown in
www.ti.com Peripheral Architecture 2 Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices andsupports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibilitythrough programmable parameters such as the...
Page 12 - Figure 2. DDR2 Memory Controller Signals; Pin
DED[31:0] DDR2MemoryController DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DSDDQS[3:0] DEA[13:0] V REFSSTL DSDDQGATE[3:0] DSDDQS[3:0] DEODT[1:0] DDRSLRATE Peripheral Architecture www.ti.com Figure 2. DDR2 Memory Controller Signals Table 1. DDR2 Memory Controller Signal...
Page 13 - Table 2; Table 2. DDR2 SDRAM Commands; Command; Table 3. Truth Table for DDR2 SDRAM Commands
www.ti.com Peripheral Architecture 2.4 Protocol Description(s) The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2 . Table 3 shows the signal truth table for the DDR2 SDRAM commands. Table 2. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row. DCA...
Page 14 - Figure 3; Figure 3. DDR2 MRS and EMRS Command
COL MRS/EMRS BANK DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDCAS DBA[2:0] DEA[13:0] Peripheral Architecture www.ti.com 2.4.1 Mode Register Set (MRS and EMRS) DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory foroperation. These registers control burst type, b...
Page 15 - Refresh Mode; Figure 4; Figure 4. Refresh Command
REFR DDR2CLKOUTDDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:0] www.ti.com Peripheral Architecture 2.4.2 Refresh Mode The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device ( Figure 4 ). REFR is automatically preceded by a DCAB command, ensuring the deac...
Page 16 - is incurred before a; Figure 5. ACTV Command
ACTV BANK ROW DDR2CLKOUTDDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:0] Peripheral Architecture www.ti.com 2.4.3 Activation (ACTV) The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write toa closed row of memory. The ACTV command o...
Page 17 - Figure 6; Figure 6. DCAB Command
DCAB DDR2CLKOUTDDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:11, 9:0] DEA[10] www.ti.com Peripheral Architecture 2.4.4 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller orfollowing the initialization ...
Page 18 - Figure 7; Figure 7. DEAC Command
DEAC DDR2CLKOUTDDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:11, 9:0] DEA[10] Peripheral Architecture www.ti.com The DEAC command closes a single bank of memory specified by the bank select signals. Figure 7 shows the timings diagram for a DEAC command. Figure 7. DEAC Comman...
Page 19 - READ Command; Figure 8; Figure 8. DDR2 READ Command
DED[31:0] DSDDQS[3:0] COL BANK DEA[10] CAS Latency D0 D1 D2 D3 D4 D5 D6 D7 DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:0] www.ti.com Peripheral Architecture 2.4.5 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The...
Page 20 - Figure 9; Figure 9. DDR2 WRT Command; Memory Width, Byte Alignment, and Endianness; Table 4; Table 4. Addressable Memory Ranges; Memory Width
DED[31:0] DSDDQS[3:0] COL BANK DQM7 Sample D0 D1 D2 D3 D4 D5 D6 D7 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8 Write Latency DEA[10] DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:0] Peripheral Architecture www.ti.com 2.4.6 Write (WRT) Command Prior to a WRT command, the de...
Page 21 - right aligned on the data bus.; Figure 10. Byte Alignment; is the memory width in bytes. Similarly, byte lane N is addresses as; Address Mapping; Table 5; Table 5. Bank Configuration Register Fields for Address Mapping; Bit Field
DDR2 memory controller data bus DED[31:24] (Byte Lane 3) DED[23:16] (Byte Lane 2) DED[15:8] (Byte Lane 1) DED[7:0] (Byte Lane 0) 32-bit memory device 16-bit memory device www.ti.com Peripheral Architecture Figure 10 shows the byte lanes used on the DDR2 memory controller. The external memory is alwa...
Page 22 - and
Peripheral Architecture www.ti.com Figure 11 and Figure 12 show how the logical address bits map to the row, column, bank, and chip select bits all combinations of IBANK and PAGESIZE values. Note that the upper three bits of the logical addresscannot be used for memory addressing, as the DDR2 memory...
Page 24 - DDR2 Memory Controller Interface; Table 6; Table 6. DDR2 Memory Controller FIFO Description; FIFO
0 1 2 3 M Bank 0 Row 0 Row 1 Row 2 Row N C o l l C o l C o l C o Row 0 Row N Row 1 Row 2 C C Bank 1 l l 0 2 1 o o C C l l 3 M o o Row 0 Row N Row 1 Row 2 C C Bank 2 l l 0 2 1 o o l l l l Row N Row 2 Row 0 Row 1 Bank P 0 1 2 3 M C C l l 3 M o o o C o C o C o C Peripheral Architecture www.ti.com Figur...
Page 25 - Figure 15. DDR2 Memory Controller FIFO Block Diagram; Selects the oldest command
Command/Data Scheduler Command FIFO Write FIFO Read FIFO Registers Commandto Memory Write Datato Memory Read DatafromMemory CommandData EDMA BUS www.ti.com Peripheral Architecture Figure 15. DDR2 Memory Controller FIFO Block Diagram 2.7.1 Command Ordering and Scheduling, Advanced Concept The DDR2 me...
Page 26 - reached; Command Starvation
Peripheral Architecture www.ti.com Next, the DDR2 memory controller examines each of the commands selected by the individual mastersand performs the following reordering: • Among all pending reads, selects reads to rows already open. Among all pending writes, selects writesto rows already open. • Se...
Page 27 - Possible Race Condition; Refresh Scheduling; Table 7; Table 7. Refresh Urgency Levels; Urgency Level
www.ti.com Peripheral Architecture 2.7.3 Possible Race Condition A race condition may exist when certain masters write data to the DDR2 memory controller. For example,if master A passes a software message via a buffer in DDR2 memory and does not wait for indication thatthe write completes, when mast...
Page 28 - Reset Considerations; Table 8; Table 8. Device and DDR2 Memory Controller Reset Relationship; Effect; DDR2 SDRAM Memory Initialization
Peripheral Architecture www.ti.com 2.9 Self-Refresh Mode Setting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the DDR2memory controller to place the external DDR2 SDRAM in a low-power mode (self refresh), in which theDDR2 SDRAM maintains valid data while consum...
Page 29 - DDR2 SDRAM Device Mode Register Configuration Values; Table 9; Table 9. DDR2 SDRAM Mode Register Configuration
www.ti.com Peripheral Architecture • Following a write to the two least-significant bytes in the SDRAM configuration register (SDCFG); see Section 2.11.3 . At the end of the initialization sequence, the DDR2 memory controller performs an auto-refresh cycle,leaving the DDR2 memory controller in an id...
Page 30 - DDR2 SDRAM Initialization After Reset; value needed to meet the DDR2 SDRAM device timings.; Interrupt Support; The DDR2 memory controller does not generate any interrupts.; EDMA Event Support
Peripheral Architecture www.ti.com 2.11.2 DDR2 SDRAM Initialization After Reset After a hard or a soft reset, the DDR2 memory controller will automatically start the initialization sequence.The DDR2 memory controller will use the default values in the SDRAM timing 1 and timing 2 registers andthe SDR...
Page 31 - Using the DDR2 Memory Controller; Connecting the DDR2 Memory Controller to DDR2 SDRAM; show a high-level view of the three memory topologies
www.ti.com Using the DDR2 Memory Controller 3 Using the DDR2 Memory Controller The following sections show various ways to connect the DDR2 memory controller to DDR2 memorydevices. The steps required to configure the DDR2 memory controller for external memory access arealso described. 3.1 Connecting...
Page 32 - Figure 16. Connecting to Two 16-Bit DDR2 SDRAM Devices
DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDWE DSDRAS DSDCAS DSDDQM0 DSDDQM1 DSDDQS0 DSDDQS1 DBA[2:0] DEA[13:0] DED[15:0] ODT0 DSDDQS0 DSDDQS1 CK CK CKE CS WE RAS CAS LDM LDQS UDQS BA[2:0] A[12:0] DQ[15:0] ODT V REF LDQS UDQS DDR2 Memory x16-bit DDR2 Memory Controller ODT1 DSDDQGATE0 (A) DSDDQGATE1 (A) DSD...
Page 33 - Figure 17. Connecting to a Single 16-Bit DDR2 SDRAM Device
DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDWE DSDRAS DSDCAS DSDDQM0 DSDDQM1 DSDDQS0 DSDDQS1 DBA[2:0] DEA[13:0] DED[15:0] V REFSSTL ODT0 DSDDQS0 DSDDQS1 CK CK CKE CS WE RAS CAS LDM UDM LDQS UDQS BA[2:0] A[12:0] DQ[15:0] ODT V REF LDQS UDQS DDR2 Memory x16-bit V REF DDR2 Memory Controller ODT1 DSDDQGATE0 (A...
Page 34 - DQS; Figure 18. Connecting to Two 8-Bit DDR2 SDRAM Devices
DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDWE DSDRAS DSDCAS DSDDQM0 DSDDQM1 DSDDQS0 DSDDQS1 DBA[2:0] DEA[13:0] DED[7:0] V REFSSTL ODT0 DSDDQS0 DSDDQS1 CK CK CKE CS WE RAS CAS DM DQS RDQS BA[2:0] A[13:0] DQ[7:0] ODT DQS RDQS DDR2 Memory x8-bit V REF DDR2 Memory Controller ODT1 DSDDQGATE0 (A) DSDDQGATE1 (A)...
Page 35 - , where each device has the; Programming the SDRAM Configuration Register (SDCFG); Field; Programming the SDRAM Refresh Control Register (SDRFC); memory refresh period
www.ti.com Using the DDR2 Memory Controller 3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. Thisprovides the DDR2 memory controller with the flexibility to interface with ...
Page 36 - displays the DDR2-533 refresh rate specification.; Table 12. DDR2 Memory Refresh Specification; shows the resulting SDRFC configuration.; Table 13. SDRFC Configuration; Table 14. SDTIM1 Configuration
Using the DDR2 Memory Controller www.ti.com Table 12 displays the DDR2-533 refresh rate specification. Table 12. DDR2 Memory Refresh Specification Symbol Description Value t REF Average Periodic Refresh Interval 7.8 μ s Therefore, the value for the REFRESH-RATE can be calculated as follows: REFRESH_...
Page 37 - Table 15. SDTIM2 Configuration
www.ti.com Using the DDR2 Memory Controller Table 15. SDTIM2 Configuration DDR2 SDRAM Data Register Field Sheet Parameter Data Sheet Formula (Register Field Name Name Description Value Field Must Be ≥ ) Value T_ODT t AOND t AOND specifies the ODT turn-on 2 (t CK cycles) t AOND 2 delay T_XSNR t XSNR ...
Page 38 - DDR2 Memory Controller Registers; Table 17. DDR2 Memory Controller Registers; Offset
DDR2 Memory Controller Registers www.ti.com 4 DDR2 Memory Controller Registers Table 17 lists the memory-mapped registers for the DDR2 memory controller. For the memory address of these registers, see the device-specific data manual. Table 17. DDR2 Memory Controller Registers Offset Acronym Register...
Page 39 - The Module ID and Revision register (MIDR) is shown in; Table 18. Module ID and Revision Register (MIDR) Field Descriptions; Bit
www.ti.com DDR2 Memory Controller Registers 4.1 Module ID and Revision Register (MIDR) The Module ID and Revision register (MIDR) is shown in Figure 19 and described in Table 18 . Figure 19. Module ID and Revision Register (MIDR) 31 30 29 16 Reserved MOD_ID R-0x0 R-0x0031 15 8 7 0 MJ_REV MN_REV R-0x...
Page 40 - DDR2 Memory Controller Status Register (DMCSTAT); The DDR2 memory controller status register (DMCSTAT) is shown in
DDR2 Memory Controller Registers www.ti.com 4.2 DDR2 Memory Controller Status Register (DMCSTAT) The DDR2 memory controller status register (DMCSTAT) is shown in Figure 20 Figure 20. DDR2 Memory Controller Status Register (DMCSTAT) 31 30 29 16 BE Rsvd Reserved R-0x0 R-0x1 R-0x0 15 3 2 1 0 Reserved I...
Page 41 - . The SDCFG register is shown in; Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions
www.ti.com DDR2 Memory Controller Registers 4.3 SDRAM Configuration Register (SDCFG) The SDRAM configuration register (SDCFG) contains fields that program the DDR2 memory controller tomeet the specification of the DDR2 memory. These fields configure the DDR2 memory controller to matchthe data bus wi...
Page 43 - The SDRFC is shown in
www.ti.com DDR2 Memory Controller Registers 4.4 SDRAM Refresh Control Register (SDRFC) The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to: • Enter and Exit the self-refresh state. • Meet the refresh requirement of the attached DDR2 device by programming the...
Page 44 - and described in; Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions
DDR2 Memory Controller Registers www.ti.com 4.5 SDRAM Timing 1 Register (SDTIM1) The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the ACtiming specification of the DDR2 memory. Note that DDR2CLKOUT is equal to the period of theDDR2CLKOUT signal. For informat...
Page 46 - Table 23. SDRAM Timing 2 Register (SDTIM2) Field Descriptions
DDR2 Memory Controller Registers www.ti.com 4.6 SDRAM Timing 2 Register (SDTIM2) Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (SDTIM2) also configures theDDR2 memory controller to meet the AC timing specification of the DDR2 memory. For information on theappropriate values ...
Page 48 - DDR2 Memory Controller Control Register (DMCCTL)
DDR2 Memory Controller Registers www.ti.com 4.8 DDR2 Memory Controller Control Register (DMCCTL) The DDR2 memory controller control register (DMCCTL) resets the interface logic of the DDR2 memorycontroller. The DMCCTL is shown in Figure 26 and described in Table 25 . Figure 26. DDR2 Memory Controlle...
Page 49 - Revision History; See
www.ti.com Revision History Revision History This revision history highlights the technical changes made to the document in this revision. See Additions/Modifications/Deletions Table 1 Modified Description for DEODT[1:0] Pins Table 10 Modified Descriptions for Bits 6 and 2 Figure 16 Modified ODT pin...
Page 50 - IMPORTANT NOTICE; Products
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...
