Texas Instruments TMS320DM357 - Manual

Texas Instruments TMS320DM357

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Table of Contents:

  • Page 3 – Contents; Preface
  • Page 5 – Appendix A Revision History
  • Page 11 – Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; Enter the literature number in the
  • Page 12 – Notational Conventions; — TMS320DM357 DMSoC Host Port Interface (HPI) Reference Guide.
  • Page 13 – — TMS320DM357 DMSoC DDR2 Memory Controller User's Guide.; SPRUGH2; — TMS320DM357 DMSoC Peripherals Overview Reference Guide.; SPRUGH3; — TMS320DM357 DMSoC Universal Serial Bus Controller User's Guide.
  • Page 14 – Introduction; Purpose of the Peripheral; The USB has the following features:
  • Page 15 – Functional Block Diagram; The USB functional block diagram is shown in; Figure 1. Functional Block Diagram
  • Page 16 – Supported Use Case Examples; The USB supports the following user cases:
  • Page 17 – An example of how to program the USB Endpoints in peripheral mode
  • Page 18 – An example of how to program the USB endpoints in host mode
  • Page 19 – Example 3. Programming the USB Endpoints in Host Mode (continued)
  • Page 20 – An example of how to do host negotiation to support USB
  • Page 22 – Industry Standard(s) Compliance Statement
  • Page 23 – Clock Control; Peripheral Architecture; The USB controller provides the following I/O signals.; For detailed information about the USB controller registers, see
  • Page 24 – USB Controller Host and Peripheral Modes Operation; The start address of the FIFO within the RAM block
  • Page 25 – Figure 2. Interrupt Service Routine Flow Chart
  • Page 26 – USB Controller Peripheral Mode Operation; Peripheral Mode: Control Transactions; Soft connect
  • Page 28 – Read Requests
  • Page 29 – Endpoint 0 States; Figure 3; Figure 3. CPU Actions at Transfer Phases
  • Page 30 – Figure 4. Sequence of Transfer
  • Page 31 – Endpoint 0 Service Routine; An Endpoint 0 interrupt is generated when:
  • Page 32 – Figure 5. Service Endpoint 0 Flow Chart
  • Page 33 – IDLE Mode; Figure 6; Figure 6. IDLE Mode Flow Chart
  • Page 34 – TX Mode; Figure 7; Figure 7. TX Mode Flow Chart
  • Page 35 – RX Mode; Figure 8; Figure 8. RX Mode Flow Chart
  • Page 36 – Error Handling; Stall Issued to Control Transfers
  • Page 37 – Bulk Transactions; Peripheral Mode: Bulk In Transactions; Setup; Table 2
  • Page 38 – Peripheral Mode: Bulk OUT Transactions; Operation
  • Page 39 – Table 3
  • Page 40 – Interrupt Transactions
  • Page 41 – Isochronous Transactions; Isochronous IN Transactions; Table 4
  • Page 42 – Isochronous OUT Transactions
  • Page 43 – Table 5
  • Page 44 – USB Controller Host Mode Operation; Host Mode: Control Transactions; Entry into Suspend mode
  • Page 45 – Setup Phase; For the SETUP Phase of a control transaction (; These bits must be set together.; Figure 9. Setup Phase of a Control Transaction Flow Chart
  • Page 46 – IN Data Phase; For the IN Data Phase of a control transaction (
  • Page 47 – OUT Data Phase; Figure 10. IN Data Phase Flow Chart; For the OUT Data Phase of a control transaction (
  • Page 48 – Figure 11. OUT Data Phase Flow Chart
  • Page 49 – IN Status Phase (following SETUP Phase or OUT Data Phase); For the IN Status Phase of a Control Transaction (; Figure 12. Completion of SETUP or OUT Data Phase Flow Chart
  • Page 50 – OUT Status Phase (following IN Data Phase); If RxPktRdy has been set, the CPU should simply clear RxPktRdy.; These bits need to be set together.
  • Page 51 – Figure 13. Completion of IN Data Phase Flow Chart
  • Page 52 – Host Mode: Bulk IN Transactions; Before initiating any Bulk IN Transactions in Host mode:
  • Page 53 – Bulk OUT Transactions; Before initiating any bulk OUT transactions:
  • Page 54 – Host Mode: Interrupt Transactions
  • Page 55 – Host Mode: Isochronous IN Transactions; Before initiating an Isochronous IN Transactions in Host mode:
  • Page 56 – Host Mode: Isochronous Out Transactions; Before initiating any Isochronous OUT transactions:
  • Page 57 – DMA Operation; DMA Transmit Operation; Transmit Buffer; Pointer to the data buffer
  • Page 58 – Four Words of Transmit Buffer Descriptor are described below.; Table 6. Transmit Buffer Descriptor Word 0
  • Page 59 – Transmit DMA State; The following information is stored in the Tx DMA State:
  • Page 60 – Figure 14. Tx Queue Flow Chart; Write the Buffer Length with the number of bytes in the buffer
  • Page 61 – Transparent Mode and RNDIS Mode Transmit DMA Operation
  • Page 62 – DMA Channel TearDown; DMA Receive Operation; Receive Buffer; RNDIS Mode Setup; EN bit of; Transparent Mode Setup; endpoint to be torn down.
  • Page 63 – CPPI Receive Buffer Descriptor; Table 10. Receive Buffer Descriptor Word 0; Table 11. Receive Buffer Descriptor Word 1; Table 12. Receive Buffer Descriptor Word 2
  • Page 64 – Receive DMA State; Table 13. Receive Buffer Descriptor Word 3
  • Page 65 – Figure 15. Rx Queue Flow Chart; The software constructs receive queue in memory.
  • Page 66 – Set the EOP bit in the packet’s EOP buffer descriptor.
  • Page 68 – DMA Teardown Procedure; Interrupt Handling; CTRLR.RNDIS bit field should be cleared to zero.; Table 14. Interrupts Generated by the USB Controller; The nine USB interrupt conditions are listed in; Table 15. USB Interrupt Conditions
  • Page 70 – Test Modes
  • Page 72 – The test procedure is as follows:
  • Page 74 – Reset Considerations; Software Reset Considerations; Interrupt Support; TMS320DMxxx DMSoC ARM Subsystem Reference Guide
  • Page 75 – Registers
  • Page 82 – and described in
  • Page 84 – The Auto Request Register (AUTOREQ) is shown in
  • Page 85 – The USB Interrupt Source Register (INTSRCR) is shown in
  • Page 86 – USB Interrupt Source Set Register (INTSETR); The USB Interrupt Source Set Register (INTSETR) is shown in
  • Page 87 – USB Interrupt Source Clear Register (INTCLRR); The USB Interrupt Source Clear Register (INTCLRR) is shown in
  • Page 88 – The USB Interrupt Mask Register (INTMSKR) is shown in; Table 24. USB Interrupt Mask Register (INTMSKR) Field Descriptions
  • Page 89 – USB Interrupt Mask Set Register (INTMSKSETR); The USB Interrupt Mask Set Register (INTMSKSETR) is shown in
  • Page 90 – The USB Interrupt Mask Clear Register (INTMSKCLRR) is shown in
  • Page 91 – The USB Interrupt Source Masked Register (INTMASKEDR) is shown in
  • Page 92 – The USB End of Interrupt Register (EOIR) is shown in; Table 28. USB End of Interrupt Register (EOIR) Field Descriptions; The USB Interrupt Vector Register (INTVECTR) is shown in
  • Page 93 – The Transmit CPPI Control Register (TCPPICR) is shown in
  • Page 94 – The CPPI DMA End of Interrupt Register (CPPIEOIR) is shown in
  • Page 95 – The Transmit CPPI Masked Status Register (TCPPIMSKSR) is shown in
  • Page 96 – and described
  • Page 97 – The Receive CPPI Control Register (RCPPICR) is shown in
  • Page 98 – Receive CPPI Interrupt Enable Set Register (RCPPIENSETR); The Receive CPPI Raw Status Register (RCPPIRAWSR) is shown in
  • Page 99 – Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR)
  • Page 100 – The Receive Buffer Count 1 Register (RBUFCNT1) is shown in
  • Page 101 – The Receive Buffer Count 3 Register (RBUFCNT3) is shown in
  • Page 102 – The Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) is shown in
  • Page 103 – The Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) is shown in
  • Page 104 – The Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) is shown in
  • Page 105 – The Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) is shown in
  • Page 107 – The Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) is shown in
  • Page 109 – The Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) is shown in; The Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) is shown in
  • Page 110 – The Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) is shown in
  • Page 111 – The Function Address Register (FADDR) is shown in; Table 61. Function Address Register (FADDR) Field Descriptions; The Power Management Register (POWER) is shown in; Table 62. Power Management Register (POWER) Field Descriptions
  • Page 112 – Interrupt Register for Receive Endpoints 1 to 4 (INTRRX); and; Field Descriptions
  • Page 113 – Figure 63. Interrupt Register for Receive Endpoints 1 to 4 (INTRRX); The Interrupt Enable Register for INTRTX (INTRTXE) is shown in
  • Page 115 – Figure 66. Interrupt Register for Common USB Interrupts (INTRUSB)
  • Page 116 – The Interrupt Enable Register for INTRUSB (INTRUSBE) is shown in
  • Page 117 – The Frame Number Register (FRAME) is shown in
  • Page 118 – The Register to Enable the USB 2.0 Test Modes (TESTMODE) is shown in
  • Page 128 – The Count 0 Register (COUNT0) is shown in; Table 81. Receive Count Register (RXCOUNT) Field Descriptions
  • Page 132 – The configuration data register (CONFIGDATA) is shown in
  • Page 134 – Transmit and Receive FIFO Register for Endpoint 0 (FIFO0); Figure 88. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)
  • Page 135 – Figure 89. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1); Figure 90. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)
  • Page 136 – Figure 91. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3); Figure 92. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)
  • Page 137 – The OTG Device Control Register (DEVCTL) is shown in; Table 94. OTG Device Control Register (DEVCTL) Field Descriptions
  • Page 138 – Table 96. Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions
  • Page 140 – Table 100. Transmit Hub Address (TXHUBADDR) Field Descriptions
  • Page 141 – Table 103. Receive Hub Address (RXHUBADDR) Field Descriptions
  • Page 143 – Appendix A
  • Page 144 – IMPORTANT NOTICE
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TMS320DM357 DMSoC Universal Serial Bus
(USB) Controller

User's Guide

Literature Number: SPRUGH3

November 2008

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Summary

Page 3 - Contents; Preface

Contents Preface ....................................................................................................................................... 11 1 Introduction ....................................................................................................................... 14 1.1 Pu...

Page 5 - Appendix A Revision History

www.ti.com 4.66 Type Register (Host mode only) (HOST_TYPE0) ................................................................ 129 4.67 Transmit Type Register (Host mode only) (HOST_TXTYPE) ................................................... 129 4.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0...

Page 11 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; Enter the literature number in the

Preface SPRUGH3 – November 2008 Read This First About This Manual This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the su...

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