Page 2 - Table of Contents
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table of Contents EMIF big endian mode correctness 60 . . . . . . . . . . . . . . . . bootmode 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset 60 . . . . . . . . . ...
Page 3 - REVISION HISTORY; Pin A12 connected directly to CV; DD; Pin B11 connected directly to V; ss
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 REVISION HISTORY The TMS320C6712D device-specific documentation has been split from TMS320C6712, TMS320C6712C,TMS320C6712D Floating−Point Digital Signal Processors, literature number SPRS148L, into a s...
Page 6 - description; members of the floating-point DSP family in the TMS320C6000
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 description The TMS320C67x DSP (including the TMS320C6712, TMS320C6712C, TMS320C6712D devices † ) are members of the floating-point DSP family in the TMS320C6000 DSP platform. The C6712, C6712C, an...
Page 7 - device characteristics; DSP device part numbers and part numbering, see Figure 5.; Table 1. Characteristics of the C6712D Processor
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device characteristics Table 1 provides an overview of the DSP. The table shows significant features of the device, including thecapacity of on-chip RAM, the peripherals, the execution time, and the pa...
Page 8 - device compatibility
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device compatibility The TMS320C6712 and C6211/C6711 devices are pin-compatible; thus, making new system designs easierand providing faster time to market. The following list summarizes the device char...
Page 9 - functional block and CPU (DSP core) diagram
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block and CPU (DSP core) diagram Enhanced DMA Controller (16 channel) Test C67x CPU (DSP Core) Data Path B B Register File Instruction Fetch Instruction Dispatch Instruction Decode Data Path...
Page 12 - memory map summary; Table 2. Memory Map Summary
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 memory map summary Table 2 shows the memory map address ranges of the device. Internal memory is always located at address0 and can be used as both program and data memory. The configuration registers...
Page 13 - peripheral register descriptions; Table 3. EMIF Registers
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 13 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 peripheral register descriptions Table 3 through Table 13 identify the peripheral registers for the device by their register names, acronyms, andhex address or hex address range. For more detailed inf...
Page 14 - peripheral register descriptions (continued); Table 5. Interrupt Selector Registers
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 peripheral register descriptions (continued) Table 5. Interrupt Selector Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 019C 0000 MUXH Interrupt multiplexer high Selects which interrupts d...
Page 15 - Table 8. EDMA Registers
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 15 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 peripheral register descriptions (continued) For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 2. 31 0 EDMA Parameter Word 0 EDMA Channel Options Parameter (OPT) ...
Page 16 - Table 10. PLL Controller Registers
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 peripheral register descriptions (continued) Table 10. PLL Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B7 C000 PLLPID Peripheral identification register (PID) [0x00010801 for PLL Co...
Page 17 - Table 12. Timer 0 and Timer 1 Registers
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 17 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 peripheral register descriptions (continued) Table 12. Timer 0 and Timer 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS TIMER 0 TIMER 1 ACRONYM REGISTER NAME COMMENTS 0194 0000 0198 0000...
Page 18 - signal groups description
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 signal groups description TRST EXT_INT7‡ IEEE Standard 1149.1 (JTAG) Emulation Reserved Reset and Interrupts Control/Status TDI TDO TMS TCK EMU0EMU1 NMI EXT_INT6‡EXT_INT5‡EXT_INT4‡ RESET Clock/PLL CLK...
Page 19 - Figure 4. Peripheral Signals
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 19 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 signal groups description (continued) TOUT1 CLKX1 FSX1 DX1 CLKR1 FSR1DR1† CLKS1† TOUT0 CLKX0FSX0DX0 CLKR0FSR0DR0 CLKS0 Timer 1 Receive Receive Timer 0 Timers McBSP1 McBSP0 Transmit Transmit Clock Cloc...
Page 21 - Table 14. Device Configurations Pins at Device Reset
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 21 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table 14. Device Configurations Pins at Device Reset (LENDIAN, EMIFBE, BOOTMODE[1:0], and CLKMODE0) CONFIGURATION PIN GDP/ZDP FUNCTIONAL DESCRIPTION EMIFBE C15 EMIF Big Endian mode correctness (EMIFBE...
Page 22 - DEVCFG register description
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 DEVICE CONFIGURATIONS (CONTINUED) DEVCFG register description The device configuration register (DEVCFG) allows the user control of the EMIF input clock source. For moredetailed information on the DEV...
Page 23 - TERMINAL FUNCTIONS
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 23 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TERMINAL FUNCTIONS The terminal functions table identifies the external signal names, the associated pin (ball) numbers along withthe mechanical package designator, the pin type (I, O/Z, or I/O/Z), wh...
Page 24 - Terminal Functions
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions SIGNAL PIN NO. TYPE† IPD/ ‡ DESCRIPTION SIGNAL NAME GDP/ ZDP TYPE† IPD/ IPU‡ DESCRIPTION CLOCK/PLL CLKIN A3 I IPU Clock Input CLKOUT2 Y12 O/Z IPD The CLKOUT2 pin is multiplexed with...
Page 36 - development support; DSP platform, including tools to
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 development support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm...
Page 37 - device support; Device development evolutionary flow:
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 37 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device support device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSPdevices and support tools. E...
Page 38 - device and development-support tool nomenclature (continued)
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device and development-support tool nomenclature (continued) PREFIX DEVICE SPEED RANGE TMS 320 C 6712D GDP 150 DEVICE FAMILY TECHNOLOGY PACKAGE TYPE†‡§ C = CMOS DEVICE TEMPERATURE RANGE (DEFAULT: 0 ° ...
Page 39 - documentation support; Extensive documentation supports all TMS320
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 39 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 documentation support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available i...
Page 40 - CPU CSR register description; CPU ID
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 CPU CSR register description The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16−31) as well as thestatus of the device power-down modes [PWRD field (bits 15−10)], p...
Page 41 - Table 17. CPU CSR Register Bit Field Description
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 41 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 CPU CSR register description (continued) Table 17. CPU CSR Register Bit Field Description BIT # NAME DESCRIPTION 31:24 CPU ID CPU ID + REV ID. Read only.Identifies which CPU is used and defines the si...
Page 42 - cache configuration (CCFG) register description; The device includes an enhancement to the; cache configuration (; Reserved; Table 18. CCFG Register Bit Field Description
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 cache configuration (CCFG) register description The device includes an enhancement to the cache configuration ( CCFG) register. A “P” bit (CCFG.31) allows the programmer to select the priority of acce...
Page 43 - interrupt sources and interrupt selector; Table 19. DSP Interrupts
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 43 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 interrupt sources and interrupt selector The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 19. The highest priority interruptis INT_00 (dedicated to RESET) while the lowe...
Page 44 - EDMA module and EDMA selector; Table 21. EDMA Channels
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 EDMA module and EDMA selector The C67x EDMA for this device also supports up to 16 EDMA channels. Four of the sixteen channels (channels8−11) are reserved for EDMA chaining, leaving 12 EDMA channels a...
Page 45 - EDMA module and EDMA selector (continued)
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 45 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 EDMA module and EDMA selector (continued) Table 23. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3) ESEL0 Register (0x01A0 FF00) 31 30 29 28 27 24 23 22 21 20 19 16 Reserved EVTSEL3 Reserved E...
Page 46 - PLL and PLL controller; Figure 8. PLL and Clock Generator Logic
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PLL and PLL controller The TMS320C6712D includes a PLL and a flexible PLL controller peripheral consisting of a prescaler (D0) andfour dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to...
Page 47 - Table 25. PLL Lock and Reset Times
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 47 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PLL and PLL controller (continued) The PLL Reset Time is the amount of wait time needed when resetting the PLL (writing PLLRST=1), in orderfor the PLL to properly reset, before bringing the PLL out of...
Page 48 - Table 27. PLL Clock Frequency Ranges
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PLL and PLL controller (continued) Table 27. PLL Clock Frequency Ranges †‡ CLOCK SIGNAL GDP 150and ZDP 150 UNIT CLOCK SIGNAL MIN MAX UNIT PLLREF (PLLEN = 1) 12 100 MHz PLLOUT 140 600 MHz SYSCLK1 − Dev...
Page 51 - DxEN
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 51 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PLL and PLL controller (continued) PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers (0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively) 31 28 27 24 23 20 19 16 Reserved R−0 15 14 12...
Page 52 - OSCDIV1
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PLL and PLL controller (continued) OSCDIV1 Register (0x01B7 C124) 31 28 27 24 23 20 19 16 Reserved R−0 15 14 12 11 8 7 5 4 3 2 1 0 OD1EN Reserved OSCDIV1 R/W−1 R−0 R/W−0 0111 Legend: R = Read only, R/...
Page 53 - where “x” represents one of the 7 through 4, or 2 GPIO pins
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 53 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 general-purpose input/output (GPIO) To use the GP[7:4, 2] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register andthe GPxDIR bits in the GP Direction (GPDIR) Register must ...
Page 54 - power-down mode logic; Figure 11 shows the power-down mode logic.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 power-down mode logic Figure 11 shows the power-down mode logic. PWRD Internal Clock Tree CPU IFR IER CSR PD1 PD2 Power- Down Logic Clock PLL CLKIN RESET PD3 Internal Peripherals Clock and Dividers Di...
Page 55 - Figure 12. PWRD Field of the CSR Register
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 55 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 31 16 15 14 13 12 11 10 9 8 Reserved Enable or Non-Enabled Interrupt Wake Enabled Interrupt Wake PD3 PD2 PD1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 0 Legend: R/W−x = Read/write reset valueNOTE: The sha...
Page 56 - Table 32. Characteristics of the Power-Down Modes; power-supply sequencing; second) if the other supply is below the proper operating voltage.; system-level design considerations
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table 32. Characteristics of the Power-Down Modes PRWD FIELD (BITS 15−10) POWER-DOWN MODE WAKE-UP METHOD EFFECT ON CHIP’S OPERATION 000000 No power-down — — 001001 PD1 Wake by an enabled interrupt CPU...
Page 57 - Figure 13. Schottky Diode Diagram; power-supply decoupling
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 57 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 DVDD CVDD VSS C6000 DSP Schottky Diode I/O Supply Core Supply GND Figure 13. Schottky Diode Diagram Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize...
Page 58 - IEEE 1149.1 JTAG compatibility statement
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 IEEE 1149.1 JTAG compatibility statement The DSP requires that both TRST and RESET resets be asserted upon power up to be properly initialized. WhileRESET initializes the DSP core, TRST initializes th...
Page 59 - EMIF device speed; Table 33. Example Boards and Maximum EMIF Speed
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 59 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 EMIF device speed The maximum EMIF speed on the device is 100 MHz. TI recommends utilizing I/O buffer informationspecification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed i...
Page 60 - EMIF big endian mode correctness; bootmode; The C6712D has two types of boot mode:; reset
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 EMIF big endian mode correctness The device Endian mode pin (LENDIAN) selects the endian mode of operation (little endian or big endian) forthe device. Little endian is the default setting. When Big E...
Page 61 - recommended operating conditions
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 61 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating case temperature range (unless otherwise noted) † Supply voltage range, CV DD (see Note 2): − 0.3 V to 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . ....
Page 63 - PARAMETER MEASUREMENT INFORMATION; Figure 15. Test Load Circuit for AC Timing Measurements; signal transition levels; IL; IH; MIN for input clocks, and; OL; MAX and V; OH; MIN for output clocks.; Figure 17. Rise and Fall Transition Time Voltage Reference Levels
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 63 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION Transmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see note) Tester Pin Electronics Data Sheet Timing Reference Point OutputUnderTest NOTE: The data sheet provides timing at...
Page 64 - Figure 18. AC Transient Specification Rise Time; Figure 19. AC Transient Specification Fall Time
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION (CONTINUED) AC transient rise/fall time specifications Figure 18 and Figure 19 show the AC transient specifications for Rise and Fall Time. For device-specificinforma...
Page 65 - timing parameters and board routing analysis
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 65 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 timing parameters and board routing analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a goodboard design practice, such delays must always b...
Page 66 - PARAMETER MEASUREMENT INFORMATION (CONTINUED)
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION (CONTINUED) Table 34. Board-Level Timings Example (see Figure 20) NO. DESCRIPTION 1 Clock route delay 2 Minimum DSP hold time 3 Minimum DSP setup time 4 External devi...
Page 67 - Figure 21. CLKIN Timings
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 67 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN †‡§ (see Figure 21) −150 NO. PLL MODE (PLLEN = 1) BYPASS MODE (PLLEN = 0) UNIT MIN MAX MIN MAX 1 tc(CLKIN) Cycle time, CLKIN 6.7 83.3 6.7 ns 2 tw(...
Page 68 - Figure 23. CLKOUT3 Timings; timing requirements for ECLKIN; Figure 24. ECLKIN Timings
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT3 †‡ (see Figure 23) NO. PARAMETER −150 UNIT NO. PARAMETER MIN MAX UNIT 1 tc(CKO3) Cycle t...
Page 69 - Figure 25. ECLKOUT Timings
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 69 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for ECLKOUT †‡§ (see Figure 25) NO. PARAMETER −150 UNIT NO. PARAMETER MIN MAX UNIT 1 tc(EKO) Cycle t...
Page 71 - Figure 26. Asynchronous Memory Read Timing
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 71 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Not Ready Hold = 2 BE Address Read Data 2 1 2 1 2 1 2 1 5 4 3 ARDY 7 7 6 6 5 ECLKOUT CE[3:0] EA[21:2] ED[15:0] AOE/SDRAS/SSOE† ARE/SDCAS/SSA...
Page 72 - Figure 27. Asynchronous Memory Write Timing
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Not Ready Hold = 2 BE Address Write Data 10 10 9 11 9 8 9 8 9 8 7 7 6 6 ECLKOUT CEx EA[21:2] ED[31:0] BE[3:0] ARDY AOE/SDRAS/SSOE† ARE/SDCAS...
Page 74 - Figure 28. SBSRAM Read Timing; Figure 29. SBSRAM Write Timing
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) ECLKOUT CE[3:0] BE[1:0] EA[21:2] ED[15:0] ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† BE1 BE2 BE3 BE4 EA Q1 Q2 Q3 Q4 9 1 4 5 8 8 9 6 7 3 1 2 † ARE/SDCAS...
Page 77 - Figure 31. SDRAM Write Command
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 77 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SYNCHRONOUS DRAM TIMING (CONTINUED) ECLKOUT CE[3:0] BE[1:0] EA[11:2] ED[15:0] AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA12 EA[21:13] BE1 BE2 BE3 BE4 Bank Column D1 D2 D3 D4 11 8 9 5 5 5 4 2 11...
Page 79 - Figure 34. SDRAM DEAC Command; Figure 35. SDRAM REFR Command
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 79 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SYNCHRONOUS DRAM TIMING (CONTINUED) ECLKOUT CE[3:0] BE[1:0] EA[21:13] ED[15:0] EA12 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA[11:2] Bank 11 12 5 5 1 DEAC 11 12 4 4 1 † ARE/SDCAS/SSADS, AWE/SD...
Page 80 - Figure 36. SDRAM MRS Command
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SYNCHRONOUS DRAM TIMING (CONTINUED) ECLKOUT CE[3:0] BE[1:0] EA[21:2] ED[15:0] AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† MRS value 11 8 12 5 1 MRS 11 8 12 4 1 † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, an...
Page 81 - timing requirements for the HOLD/HOLDA cycles
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 81 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles † (see Figure 37) NO. −150 UNIT NO. MIN MAX UNIT 3 th(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E ns † E = ECLKIN period in ns s...
Page 82 - BUSREQ TIMING; Figure 38. BUSREQ Timing
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 82 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 BUSREQ TIMING switching characteristics over recommended operating conditions for the BUSREQ cycles(see Figure 38) NO. PARAMETER −150 UNIT NO. PARAMETER MIN MAX UNIT 1 td(EKOH-BUSRV) Delay time, ECLKO...
Page 84 - Figure 39. Reset Timing
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 RESET TIMING (CONTINUED) Phase 1 Phase 2 11 10 9 8 7 6 5 4 3 13 12 2 1 1 CLKIN ECLKIN Internal Reset Internal SYSCLK1 Internal SYSCLK2 Internal SYSCLK3 RESET Phase 3 EMIF Z Group† EMIF Low Group† Z Gr...
Page 87 - MULTICHANNEL BUFFERED SERIAL PORT TIMING
SPRS293 − OCTOBER 2005 87 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING switching characteristics over recommended operating conditions for McBSP †‡ (see Figure 41) NO. PARAMETER −150 UNIT NO. PARAMETER MIN MAX UNIT 1 td(CKSH-CKRXH) Delay time, CLKS high t...
Page 88 - MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED); Figure 41. McBSP Timings
SPRS293 − OCTOBER 2005 88 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 14 13 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 CLKS CLKR FSR (int) FSR (ext) DR CLKX FSX (int) FSX (ext) FSX (XDATDLY=00b) DX 13...
Page 95 - Figure 47. Timer Timing
SPRS293 − OCTOBER 2005 95 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TIMER TIMING timing requirements for timer inputs † (see Figure 47) NO. −150 UNIT NO. MIN MAX UNIT 1 tw(TINPH) Pulse duration, TINP high 2P ns 2 tw(TINPL) Pulse duration, TINP low 2P ns † P = 1/CPU clock frequency in ns. For ...
Page 96 - timing requirements for GPIO inputs; Figure 48. GPIO Port Timing
SPRS293 − OCTOBER 2005 96 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING timing requirements for GPIO inputs †‡ (see Figure 48) NO. −150 UNIT NO. MIN MAX UNIT 1 tw(GPIH) Pulse duration, GPIx high 4P ns 2 tw(GPIL) Pulse duration, GPIx low 4P ns † P = ...
Page 99 - PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TMS320C6712DGDP150 ACTIVE BGA GDP 272 40 TBD SNPB Level-3-220C-168HR TMS320C6712DZDP150 ACTIVE BGA ZDP 272 40 Pb-Free (RoHS) SNAGCU Level-3-260C-168HR (1) T...
Page 100 - MECHANICAL DATA; PLASTIC BALL GRID ARRAY
MECHANICAL DATA MPBG274 – MAY 2002 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GDP (S–PBGA–N272) PLASTIC BALL GRID ARRAY 2 4 6 8 20 18 16 14 12 10 M E A 1 CB D GF H KJ L W R N P UT V Y 3 5 7 9 11 17 15 13 19 0,635 0,635 26,80 SQ 23,80 24,20 SQ 27,20 24,13 TYP 0,57 0,65 0,60 0,90 Seating Plane 0,50 ...
