Texas Instruments TMS320C6454 - Manual

Texas Instruments TMS320C6454

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Table of Contents:

  • Page 2 – PRODUCT PREVIEW
  • Page 3 – Fixed-Point Digital Signal Processor
  • Page 4 – Functional Block Diagram; shows the functional block diagram of the C6454 device.
  • Page 5 – Contents
  • Page 6 – Device Overview; Device Characteristics; Table 2-1. Characteristics of the C6454 Processor; HARDWARE FEATURES
  • Page 8 – Other new features include:
  • Page 9 – Data path A
  • Page 10 – Memory Map Summary; MEMORY BLOCK DESCRIPTION
  • Page 12 – Boot Modes Supported; Supported, describes each boot mode in more detail.
  • Page 13 – nd-Level Bootloaders; such as Code Composer Studio.
  • Page 14 – Pin Map; through
  • Page 18 – Signal Groups Description
  • Page 24 – Terminal Functions; The terminal functions table (
  • Page 25 – SIGNAL
  • Page 35 – RESERVED FOR TEST
  • Page 42 – GROUND PINS
  • Page 47 – Development Support; Device development evolutionary flow:
  • Page 48 – ) or contact your TI sales representative.; Documentation Support; . Tip: Enter the literature number in the
  • Page 50 – Device Configuration at Device Reset; NOTE; CONFIGURATION
  • Page 52 – Peripheral Configuration at Device Reset
  • Page 53 – Peripheral Selection After Device Reset
  • Page 54 – Figure 3-1. Peripheral Transitions Between States
  • Page 55 – Device State Control Registers; and described in the next sections.; Table 3-5. Device State Control Registers; HEX ADDRESS RANGE
  • Page 56 – Peripheral Lock Register Description; Bit
  • Page 57 – Peripheral Configuration Register 0 Description
  • Page 59 – Peripheral Configuration Register 1 Description
  • Page 60 – Peripheral Status Registers Description
  • Page 63 – EMAC Configuration Register (EMACCFG) Description
  • Page 64 – Emulator Buffer Powerdown Register (EMUBUFPD) Description
  • Page 65 – Device Status Register Description; and
  • Page 68 – Voltage and Operating Case Temperature.
  • Page 69 – Configuration Examples
  • Page 71 – System Interconnect; Bridges perform a variety of functions:
  • Page 72 – Data Switch Fabric Connections
  • Page 73 – Figure 4-1. Switched Central Resource Block Diagram
  • Page 74 – Configuration Switch Fabric
  • Page 76 – Priority Allocation; . The priority is enforced when several
  • Page 77 – Memory Architecture; shows a block diagram of the C64x+ Megamodule.
  • Page 78 – Region 1 size is 32K bytes with no wait states.
  • Page 80 – Memory Protection; Table 5-1. Available Memory Page Protection Schemes; AID0 Bit; Memory-mapped registers configuration bus
  • Page 81 – Megamodule Resets; Megamodule, either both globally or just locally.; ). And for more detailed information on device
  • Page 82 – Megamodule Revision; and described in
  • Page 83 – Table 5-4. Megamodule Interrupt Registers
  • Page 84 – Table 5-5. Megamodule Powerdown Control Registers
  • Page 85 – Table 5-8. Megamodule Cache Configuration Registers
  • Page 89 – Table 5-10. CPU Megamodule Bandwidth Management Registers
  • Page 90 – Recommended Operating Conditions; MIN
  • Page 91 – Recommended Operating Conditions (continued)
  • Page 92 – Case Temperature (Unless Otherwise Noted)
  • Page 94 – Parameter Information; Tester Pin Electronics; Figure 7-1. Test Load Circuit for AC Timing Measurements; MAX and V; MIN for input clocks,; MAX and V; MIN for output clocks.; Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
  • Page 95 – Timing Parameters and Board Routing Analysis; buffers may be used to compensate any timing differences.; DESCRIPTION
  • Page 96 – Recommended Clock and Control Signal Transition Behavior; Power-Supply Sequencing; Power-Supply Decoupling; UNIT
  • Page 98 – EDMA3 Device-Specific Information
  • Page 99 – EDMA3 Channel Synchronization Events; Table 7-3. C6454 EDMA3 Channel Synchronization Events; EDMA
  • Page 100 – Table 7-4. EDMA3 Channel Controller Registers
  • Page 106 – Table 7-6. EDMA3 Transfer Controller 0 Registers
  • Page 107 – Table 7-7. EDMA3 Transfer Controller 1 Registers
  • Page 108 – Table 7-8. EDMA3 Transfer Controller 2 Registers
  • Page 110 – Table 7-9. EDMA3 Transfer Controller 3 Registers
  • Page 112 – Interrupt Sources and Interrupt Controller; EVENT NUMBER
  • Page 115 – External Interrupts Electrical Data/Timing; Table 7-11. Timing Requirements for External Interrupts
  • Page 116 – TYPE; The following sequence must be followed during a Power-on Reset:
  • Page 117 – all the system clocks are invalid at this point.; The following sequence must be followed during a Warm Reset:
  • Page 118 – System Reset; During a System Reset, the following happens:
  • Page 119 – Reset Priority; Maximum Reset
  • Page 120 – Reset Electrical Data/Timing; Table 7-14. Timing Requirements for Reset; For
  • Page 123 – PLL1 and PLL1 Controller; As shown in; DSP
  • Page 124 – PLL1 Controller Device-Specific Information
  • Page 125 – SYSCLK5 clocks the emulation and trace logic of the DSP.; CLOCK SIGNAL
  • Page 126 – PLL1 Controller Memory Map; The memory map of the PLL1 controller is shown in
  • Page 127 – PLL1 Controller Register Descriptions; The PLL control register (PLLCTL) is shown in
  • Page 128 – The PLL multiplier control register (PLLM) is shown in
  • Page 130 – The PLL controller divider 4 register (PLLDIV4) is shown in
  • Page 131 – The PLL controller divider 5 register (PLLDIV5) is shown in
  • Page 137 – PLL1 Controller Input and Output Clock Electrical Data/Timing; Table 7-29. Timing Requirements for CLKIN1 Devices
  • Page 138 – PLL2 and PLL2 Controller
  • Page 139 – PLL2 Controller Device-Specific Information; PLL2 is only unlocked during the power-up sequence (see
  • Page 140 – PLL2 Controller Memory Map; The memory map of the PLL2 controller is shown in
  • Page 141 – The PLL controller divider 1 register (PLLDIV1) is shown in
  • Page 145 – Table 7-38. SYSCLK Status Register Field Descriptions
  • Page 146 – PLL2 Controller Input Clock Electrical Data/Timing; Table 7-39. Timing Requirements for CLKIN2
  • Page 147 – DDR2 Memory Controller; DDR2 Memory Controller Device-Specific Information; SPRAAA7
  • Page 148 – DDR2 Memory Controller Peripheral Register Description(s); Table 7-40. DDR2 Memory Controller Registers
  • Page 149 – ZBT (Zero Bus Turnaround) SRAM and Late Write SRAM
  • Page 151 – Table 7-42. Timing Requirements for AECLKIN for EMIFA
  • Page 152 – EMIFA Module; Figure 7-32. AECLKOUT Timing for the EMIFA Module
  • Page 153 – Memory Cycles for EMIFA Module; PARAMETER; Figure 7-33. Asynchronous Memory Read Timing for EMIFA
  • Page 154 – Figure 7-34. Asynchronous Memory Write Timing for EMIFA
  • Page 155 – Programmable Synchronous Interface Timing
  • Page 158 – Cycles for EMIFA Module
  • Page 159 – for EMIFA Module (see
  • Page 163 – Table 7-52. Timing Requirements for I2C Timings
  • Page 164 – Table 7-53. Switching Characteristics for I2C Timings
  • Page 167 – Table 7-55. Timing Requirements for Host-Port Interface Cycles
  • Page 177 – The McBSP provides these functions:
  • Page 180 – Multichannel Buffered Serial Port (McBSP) Timing
  • Page 188 – Interface Modes
  • Page 189 – BALL NUMBER; Using the RMII Mode of the EMAC
  • Page 190 – Interface Mode Clocking
  • Page 194 – Table 7-73. EMAC Control Module Registers
  • Page 195 – EMAC MII and GMII Electrical Data/Timing
  • Page 202 – Transmit
  • Page 206 – Table 7-94. Timing Requirements for Timer Inputs
  • Page 207 – Section 4; Table 7-96. Default Values for PCI Configuration; DEFAULT
  • Page 208 – PCI HOST ACCESS
  • Page 209 – Table 7-98. PCI Back End Configuration Registers; DSP ACCESS
  • Page 211 – Table 7-100. PCI Hook Configuration Registers
  • Page 212 – HEX ADDRESS OFFSET
  • Page 215 – Table 7-103. Timing Requirements for GPIO Inputs
  • Page 217 – Mechanical Data; Packaging Information; AIR FLOW
  • Page 218 – SEE
  • Page 222 – PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
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PRODUCT PREVIEW

1

TMS320C6454 Fixed-Point Digital Signal Processor

1.1 Features

TMS320C6454

Fixed-Point Digital Signal Processor

SPRS311A – APRIL 2006 – REVISED DECEMBER 2006

•

32-Bit DDR2 Memory Controller (DDR2-533

•

High-Performance Fixed-Point DSP (C6454)

SDRAM)

–

1.39-, 1.17-, and 1-ns Instruction Cycle Time

•

EDMA3 Controller (64 Independent Channels)

–

720-MHz, 850-MHz, and 1-GHz Clock Rate

–

Eight 32-Bit Instructions/Cycle

•

32-/16-Bit Host-Port Interface (HPI)

–

8000 MIPS/MMACS (16-Bits)

•

32-Bit 33-/66-MHz, 3.3-V Peripheral Component

–

Commercial Temperature [0°C to 90°C]

Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.3

•

TMS320C64x+™ DSP Core
–

Dedicated SPLOOP Instruction

•

One Inter-Integrated Circuit (I

2

C) Bus

–

Compact Instructions (16-Bit)

•

Two McBSPs

–

Instruction Set Enhancements

•

10/100/1000 Mb/s Ethernet MAC (EMAC)

–

Exception Handling

–

IEEE 802.3 Compliant

•

TMS320C64x+ Megamodule L1/L2 Memory

–

Supports Multiple Media Independent

Architecture:

Interfaces (MII, GMII, RMII, and RGMII)

–

256K-Bit (32K-Byte) L1P Program Cache

–

8 Independent Transmit (TX) and

[Direct Mapped]

8 Independent Receive (RX) Channels

–

256K-Bit (32K-Byte) L1D Data Cache

•

Two 64-Bit General-Purpose Timers,

[2-Way Set-Associative]

Configurable as Four 32-Bit Timers

–

8M-Bit (1048K-Byte) L2 Unified Mapped

•

16 General-Purpose I/O (GPIO) Pins

RAM/Cache [Flexible Allocation]

•

System PLL and PLL Controller

–

256K-Bit (32K-Byte) L2 ROM

•

Secondary PLL and PLL Controller, Dedicated

–

Time Stamp Counter

to EMAC and DDR2 Memory Controller

•

Endianess: Little Endian, Big Endian

•

IEEE-1149.1 (JTAG™)

•

64-Bit External Memory Interface (EMIFA)

Boundary-Scan-Compatible

–

Glueless Interface to Asynchronous

•

697-Pin Ball Grid Array (BGA) Package

Memories (SRAM, Flash, and EEPROM) and

(ZTZ or GTZ Suffix), 0.8-mm Ball Pitch

Synchronous Memories (SBSRAM and ZBT
SRAM)

•

0.09-

µ

m/7-Level Cu Metal Process (CMOS)

–

Supports Interface to Standard Sync

•

3.3-/1.8-/1.5-V I/Os, 1.25-/1.2-V Internal

Devices and Custom Logic (FPGA, CPLD,

•

Pin-Compatible with the TMS320C6455

ASICs, etc.)

Fixed-Point Digital Signal Processor

–

32M-Byte Total Addressable External
Memory Space

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.

All trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the

Copyright © 2006–2006, Texas Instruments Incorporated

formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.

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Summary

Page 2 - PRODUCT PREVIEW

www.ti.com PRODUCT PREVIEW 1.1.1 ZTZ/GTZ BGA Package (Bottom View) ZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) A 2 B 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 27 28 29 AG AH AJ NOTE: The ZTZ mechanical p...

Page 3 - Fixed-Point Digital Signal Processor

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlierC6000 devices, two of these eight functional units are multipliers or ....

Page 4 - Functional Block Diagram; shows the functional block diagram of the C6454 device.

www.ti.com PRODUCT PREVIEW 1.3 Functional Block Diagram L2 Memory Controller (Memory Protect/ Bandwidth Mgmt) DDR2 Mem Ctlr System (B ) C64x+ DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Data Path A A Register File A31−A16 A15−A0 Device Configuration Logic .L1 .S1 .M1 xxxx ....

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