Page 6 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; . Tip: Enter the literature number in the search box; SPRUEM3
Preface SPRUEN0D – March 2011 Read This First About This Manual This document describes the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital SignalProcessor (DSP). The I2C peripheral provides an interface between the DSP and other devices that arecompliant with Philips Semiconduc...
Page 7 - Introduction; Purpose of the Peripheral; Features Not Supported
User's Guide SPRUEN0D – March 2011 Inter-Integrated Circuit (I2C) Peripheral 1 Introduction This document describes the operation of the inter-integrated circuit (I2C) peripheral in the TMS320C642xDigital Signal Processor (DSP). The scope of this document assumes that you are familiar with the Phili...
Page 8 - Functional Block Diagram; A block diagram of the I2C peripheral is shown in; Figure 1. I2C Peripheral Block Diagram; Industry Standard(s) Compliance Statement
ICXSR ICDXR ICRSR ICDRR Clock synchronizer Prescaler Noise filters Arbitrator I2C INT ICREVT Peripheral data bus Interruptto CPU Sync events toEDMA controller SDA SCL Control/status registers CPU EDMA I2C peripheral ICXEVT Introduction www.ti.com 1.3 Functional Block Diagram A block diagram of the I...
Page 9 - resistors; Peripheral Architecture; The I2C peripheral consists of the following primary blocks:; Bus Structure; Figure 1; Figure 2. Multiple I2C Modules Connected
TI device I2C I 2 C EPROM I 2 C I2C TI device V DD Pull-up resistors Serial data (SDA) Serial clock (SCL) controller www.ti.com Peripheral Architecture 2 Peripheral Architecture The I2C peripheral consists of the following primary blocks: • A serial interface: one data pin (SDA) and one clock pin (S...
Page 10 - Clock Generation; As shown in; Figure 3. Clocking Diagram for the I2C Peripheral; Prescaled Module Clock Frequency Range:
d765 PLL1 I2C prescaler Prescaled module clock−−MUST be set to 6.7 to 13.3 MHz I2C input clock External input clock Register bits (ICPSC[IPSC]) I2C clock dividers Register bits (ICCLKL[ICCL]), (ICCLKH[ICCH]) Prescaled module clock frequency = I2C input clock frequency (IPSC + 1) I2C module I2C seria...
Page 11 - Clock Synchronization; Figure 4; Signal Descriptions; Input and Output Voltage Levels
Wait state Start HIGHperiod SCL from device #1 SCL from device #2 Bus line SCL www.ti.com Peripheral Architecture The prescaler (IPSC bit in ICPSC) must only be initialized while the I2C module is in the reset state(IRS = 0 in ICMDR). The prescaled frequency only takes effect when the IRS bit in ICM...
Page 12 - Data Validity; Figure 5; START and STOP Conditions; Figure 6; Figure 6. I2C Peripheral START and STOP Conditions
Data line stable data Change of dataallowed SDA SCL SDA SCL START condition (S) condition (P) STOP Peripheral Architecture www.ti.com 2.4.2 Data Validity The data on SDA must be stable during the high period of the clock (see Figure 5 ). The high or low state of the data line, SDA, can change only w...
Page 13 - Serial Data Formats; Figure 7; Figure 7. I2C Peripheral Data Transfer; Figure 8
SDA SCL MSB Acknowledgement bit from slave (No-)Acknowledgement bit from receiver 1 2 7 8 9 1 2 8 9 Slave address ACK START condition (S) STOP condition (P) R/W ACK Data S Slave address R/W ACK Data ACK Data ACK P 7 n n 1 1 1 1 1 1 www.ti.com Peripheral Architecture 2.6 Serial Data Formats Figure 7 ...
Page 14 - 0-Bit Addressing Format; Figure 9; Free Data Format; In the free data format (; Using a Repeated START Condition
S 1 1 1 1 1 0 A A 7 A A A A A A A A ACK 0 1 1 8 ACK 1 Data n ACK 1 P 1 A A = 2 MSBs R/W 8 LSBs of slave address Data Data S 1 Data ACK ACK ACK P 1 n n n 1 1 1 1 7 n 7 n 1 1 1 1 1 1 1 1 S Slave address R/W ACK Data ACK S Slave address R/W ACK Data ACK P 1 Any number 1 Any number Peripheral Architectu...
Page 15 - Endianness Considerations; Table 1; Table 1. Operating Modes of the I2C Peripheral
www.ti.com Peripheral Architecture 2.7 Endianness Considerations When the device is configured for big-endian mode, in order for the data to be placed in the right side ofthe register being accessed, access to the I2C registers must be performed as follows:• 8-bit accesses: An offset of 3h must be a...
Page 16 - Table 2; Table 2. Ways to Generate a NACK Bit
Peripheral Architecture www.ti.com 2.9 NACK Bit Generation When the I2C peripheral is a receiver (master or slave), it can acknowledge or ignore bits sent by thetransmitter. To ignore any new bits, the I2C peripheral must send a no-acknowledge (NACK) bit during theacknowledge cycle on the bus. Table...
Page 17 - A repeated START condition and a data bit
1 0 0 0 1 0 0 0 1 1 1 1 1 0 Device #1 lost arbitration and switches off Bus line SCL Data from device #1 Data from device #2 Bus line SDA www.ti.com Peripheral Architecture 2.10 Arbitration If two or more master-transmitters simultaneously start a transmission on the same bus, an arbitrationprocedur...
Page 18 - Reset Considerations; Software Reset Considerations
Peripheral Architecture www.ti.com 2.11 Reset Considerations The I2C peripheral has two reset sources: software reset and hardware reset. 2.11.1 Software Reset Considerations To reset the I2C peripheral, write 0 to the I2C reset (IRS) bit in the I2C mode register (ICMDR). All statusbits in the I2C i...
Page 19 - SPRUEN8; Configuring the I2C in Slave Receiver and Transmitter Mode; If the I2C is able to respond to 7-bit Addressing: Configure XA = 0
www.ti.com Peripheral Architecture 2.12.1 Configuring the I2C in Master Receiver Mode and Servicing Receive Data via CPU The following initialization procedure is for the I2C controller configured in Master Receiver mode. TheCPU is used to move data from the I2C receive register to CPU memory (memor...
Page 21 - Interrupt Support; Interrupt Events and Requests; The I2C peripheral can generate the interrupts described in; Table 3. Descriptions of the I2C Interrupt Events; Interrupt Multiplexing; DMA Events Generated by the I2C Peripheral
www.ti.com Peripheral Architecture 2.13 Interrupt Support The is capable of interrupting the DSP CPU. The CPU can determine which I2C events caused theinterrupt by reading the I2C interrupt vector register (ICIVR). ICIVR contains a binary-coded interruptvector type to indicate which interrupt has oc...
Page 22 - Emulation Considerations; Registers; Table 4
Registers www.ti.com 2.16 Emulation Considerations The response of the I2C events to emulation suspend events (such as halts and breakpoints) is controlledby the FREE bit in the I2C mode register (ICMDR). The I2C peripheral either stops exchanging data(FREE = 0) or continues to run (FREE = 1) when a...
Page 23 - The I2C own address register (ICOAR) is shown in
www.ti.com Registers 3.1 I2C Own Address Register (ICOAR) The I2C own address register (ICOAR) is used to specify its own slave address, which distinguishes itfrom other slaves connected to the I2C-bus. If the 7-bit addressing mode is selected (XA = 0 in ICMDR),only bits 6-0 are used; bits 9-7 are i...
Page 24 - The I2C interrupt mask register (ICIMR) is shown in; Table 6. I2C Interrupt Mask Register (ICIMR) Field Descriptions
Registers www.ti.com 3.2 I2C Interrupt Mask Register (ICIMR) The I2C interrupt mask register (ICIMR) is used to individually enable or disable I2C interrupt requests. The I2C interrupt mask register (ICIMR) is shown in Figure 14 and described Table 6 . Figure 14. I2C Interrupt Mask Register (ICIMR) ...
Page 25 - The I2C interrupt status register (ICSTR) is shown in; Table 7. I2C Interrupt Status Register (ICSTR) Field Descriptions
www.ti.com Registers 3.3 I2C Interrupt Status Register (ICSTR) The I2C interrupt status register (ICSTR) is used to determine which interrupt has occurred and to readstatus information. The I2C interrupt status register (ICSTR) is shown in Figure 15 and described in Table 7 . Figure 15. I2C Interrup...
Page 28 - I2C Clock Divider Registers (ICCLKL and ICCLKH); and described in
Registers www.ti.com 3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) When the I2C is a master, the prescaled module clock is divided down for use as the I2C serial clock onthe SCL pin. The shape of the I2C serial clock depends on two divide-down values, ICCL and ICCH. Fordetailed information on ...
Page 29 - The data count register (ICCNT) is shown in
www.ti.com Registers 3.5 I2C Data Count Register (ICCNT) The I2C data count register (ICCNT) is used to indicate how many data words to transfer when the I2C isconfigured as a master-transmitter-receiver (MST = 1 and TRX = 1/0 in ICMDR) and the repeat mode isoff (RM = 0 in ICMDR). In the repeat mode...
Page 30 - The I2C data receive register (ICDRR) is shown in; Table 11. I2C Data Receive Register (ICDRR) Field Descriptions; Table 12. I2C Slave Address Register (ICSAR) Field Descriptions
Registers www.ti.com 3.6 I2C Data Receive Register (ICDRR) The I2C data receive register (ICDRR) is used to read the receive data. The ICDRR can receive a datavalue of up to 8 bits; data values with fewer than 8 bits are right-aligned in the D bits and the remaining Dbits are undefined. The number o...
Page 31 - The I2C data transmit register (ICDXR) is shown in; Table 13. I2C Data Transmit Register (ICDXR) Field Descriptions
www.ti.com Registers 3.8 I2C Data Transmit Register (ICDXR) The CPU or EDMA writes transmit data to the I2C data transmit register (ICDXR). The ICDXR can accepta data value of up to 8 bits. When writing a data value with fewer than 8 bits, the written data must beright-aligned in the D bits. The num...
Page 32 - The I2C mode register (ICMDR) contains the control bits of the I2C.
Registers www.ti.com 3.9 I2C Mode Register (ICMDR) The I2C mode register (ICMDR) contains the control bits of the I2C. The I2C mode register (ICMDR) is shown in shown in Figure 22 and described in Table 14 . Figure 22. I2C Mode Register (ICMDR) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 NACKMOD FREE S...
Page 35 - Table 16. How the MST and FDF Bits Affect the Role of TRX Bit
ICDRR ICRSR 0 1 ICSAR ICOAR 0 1 ICDXR ICXSR 0 1 0 0 DLB SCL_IN SCL_OUT Address/data To internal I2C logic From internal I2C logic To internal I2C logic To ARM CPU or EDMA From ARM CPU or EDMA From ARM CPU or EDMA From ARM CPU or EDMA SCL SDA I2C peripheral DLB DLB www.ti.com Registers Table 16. How ...
Page 36 - The I2C interrupt vector register (ICIVR) is shown in; Table 17. I2C Interrupt Vector Register (ICIVR) Field Descriptions
Registers www.ti.com 3.10 I2C Interrupt Vector Register (ICIVR) The I2C interrupt vector register (ICIVR) is used by the CPU to determine which event generated the I2Cinterrupt. Reading ICIVR clears the interrupt flag; if other interrupts are pending, a new interrupt isgenerated. If there are more t...
Page 37 - The I2C extended mode register (ICEMDR) is shown in; Table 18. I2C Extended Mode Register (ICEMDR) Field Descriptions
www.ti.com Registers 3.11 I2C Extended Mode Register (ICEMDR) The I2C extended mode register (ICEMDR) is used to indicate which condition generates a transmit dataready interrupt. The I2C extended mode register (ICEMDR) is shown in Figure 25 and described in Table 18 . Figure 25. I2C Extended Mode R...
Page 38 - The I2C prescaler register (ICPSC) is shown in
Registers www.ti.com 3.12 I2C Prescaler Register (ICPSC) The I2C prescaler register (ICPSC) is used for dividing down the I2C input clock to obtain the desiredprescaled module clock for the operation of the I2C. The IPSC bits must be initialized while the I2C is in reset (IRS = 0 in ICMDR). The pres...
Page 39 - The I2C peripheral identification register (ICPID1) is shown in
www.ti.com Registers 3.13 I2C Peripheral Identification Register (ICPID1) The I2C peripheral identification registers (ICPID1) contain identification data (class, revision, and type) forthe peripheral. The I2C peripheral identification register (ICPID1) is shown in Figure 27 and described in Table 2...
Page 40 - Appendix A Revision History; Table 22. Document Revision History
www.ti.com Appendix A Revision History Table 22 lists the changes made since the previous version of this document. Table 22. Document Revision History Reference Additions/Modifications/Deletions Section 1.2 Changed second bullet point. Section 3.5 Changed first sentence in first paragraph. Table 14...
Page 41 - IMPORTANT NOTICE
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...
