Texas Instruments TMS320 - Manual
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Table of Contents:
- Page 3 – description
- Page 5 – TMS320 SECOND-GENERATION; Table 1. TMS320 Second-Generation Device Overview; architecture; Branch to an address specified by the accumulator
- Page 7 – scaling shifter; PRD; memory control
- Page 8 – Figure 1. Memory Maps
- Page 9 – interrupts and subroutines; A standalone processor
- Page 10 – instruction set; addressing modes
- Page 11 – instruction set summary
- Page 12 – Table 3. TMS320C25 Instruction Set Summary
- Page 18 – development support
- Page 19 – Table 4. TMS320 Second-Generation Software and Hardware Support
- Page 20 – documentation support; Digital Signal Processing; specification overview
- Page 21 – CC; recommended operating conditions; ADV
- Page 22 – and be specified at a load capacitance of 20 pF.; Figure 2. Internal Clock Option; external clock option
- Page 24 – MEMORY AND PERIPHERAL INTERFACE TIMING
- Page 25 – HOLD TIMING
- Page 26 – SERIAL PORT TIMING
- Page 28 – , a power dissipation
- Page 29 – Figure 3. External Clock Option; Hardware Interfacing to the TMS320C25 (document number; Figure 4. Test Load Circuit
- Page 30 – Figure 5. Voltage Reference Levels
- Page 33 – EPROM PROGRAMMING; Supply voltage range, V; PP; Input voltage range on pins 24 and 25
- Page 35 – CLOCK CHARACTERISTICS AND TIMING; internal clock option; , a power dissipation of 1 mW, and be specified; Figure 6. Internal Clock Option
- Page 36 – Figure 7. External Clock Option
- Page 41 – TIMING DIAGRAMS
- Page 42 – memory read timing
- Page 43 – memory write timing
- Page 44 – one wait-state memory access timing
- Page 45 – reset timing
- Page 47 – serial port receive timing
- Page 54 – TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25; TMS320C25FNL (PLCC) reflow soldering precautions; no special handling; NOTE; Shipping tubes will not withstand the 125
- Page 55 – MECHANICAL DATA
- Page 56 – WARNING
- Page 58 – programming the TMS320E25 EPROM cell; Figure 8. EPROM Adapter Socket
- Page 60 – , filterless UV lamp will erase the device in 21 minutes. The; fast programming; can be programmed in any order.
- Page 61 – program verify; Programmed bits may be verified with V; the timing for the program and verify operation.; Figure 10. Fast Programming Flowchart
- Page 63 – Table 6. TMS320E25 Protect and Verify EPROM Mode Levels; EPROM protect
- Page 65 – Figure 13. EPROM Protect Timing
- Page 66 – INDEX
- Page 68 – PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
- Page 69 – IMPORTANT NOTICE
TMS320 SECOND-GENERATION
DIGITAL SIGNAL PROCESSORS
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1
ADVANCE INFORMATION concerns new products in the
sampling or preproduction phase of development.
Characteristic data and other specifications are subject to
change without notice.
Copyright
1991, Texas Instruments Incorporated
•
80-ns Instruction Cycle Time
•
544 Words of On-Chip Data RAM
•
4K Words of On-Chip Secure Program
EPROM (TMS320E25)
•
4K Words of On-Chip Program ROM
(TMS320C25)
•
128K Words of Data/Program Space
•
32-Bit ALU/Accumulator
•
16
×
16-Bit Multiplier With a 32-Bit Product
•
Block Moves for Data/Program
Management
•
Repeat Instructions for Efficient Use of
Program Space
•
Serial Port for Direct Codec Interface
•
Synchronization Input for Synchronous
Multiprocessor Configurations
•
Wait States for Communication to Slow
Off-Chip Memories/Peripherals
•
On-Chip Timer for Control Operations
•
Single 5-V Supply
•
Packaging: 68-Pin PGA, PLCC, and
CER-QUAD
•
68-to-28 Pin Conversion Adapter Socket for
EPROM Programming
•
Commercial and Military Versions Available
•
NMOS Technology:
— TMS32020
200-ns cycle time
. . . . . . . . .
•
CMOS Technology:
— TMS320C25
100-ns cycle time
. . . . . . . .
— TMS320E25
100-ns cycle time
. . . . . . . .
— TMS320C25-50
80-ns cycle time
. . . . . .
description
This data sheet provides complete design documentation for the second-generation devices of the TMS320
family. This facilitates the selection of the devices best suited for user applications by providing all specifications
and special features for each TMS320 member. This data sheet is divided into four major sections: architecture,
electrical specifications (NMOS and CMOS), timing diagrams, and mechanical data. In each of these sections,
generic information is presented first, followed by specific device information. An index is provided for quick
reference to specific information about a device.
1
2
3
4
5
6
7
8
9 10 11
A
B
C
D
E
F
G
H
J
K
L
68-Pin GB Package†
(Top View)
IACK
MSC
CLKOUT1
CLKOUT2
XF
HOLDA
DX
FSX
X2 CLKIN
X1
BR
D8
D9
D10
D1
1
D12
D13
D14
D15
READY
CLKR
CLKX
STRB
R/W
PS
IS
DS
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
VSS
D7
D6
D5
D4
D3
D2
D1
D0
SYNC
INT0
INT1
INT2
VCC
DR
FSR
A0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A1
1
A12
A13
A14
A15
V
SS
V
CC
V
CC
V
CC
68-Pin FN and FZ Packages†
(Top View)
ADV
ANCE INFORMA
TION
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Summary
TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 3 description The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speedcontroller with the numerical capability of an array pro...
DEVICE RAM ROM/EPROM PROG DATA TIMER CYCLE TIME (ns) TYP POWER (mW) PACKAGE TYPE I/O† TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 5 Table 1 provides an overview of the second-generation TMS320 processors with comparisons of...
TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 7 scaling shifter The TMS320C2x scaling shifter has 16-bit input connected to the data bus and a 32-bit output connected to theALU. The scaling shifter produces a left shift of 0 ...
