Texas Instruments TMS320C674X - Manual

Texas Instruments TMS320C674X

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Table of Contents:

  • Page 10 – Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; SPRUGM5
  • Page 11 – SPRUGM7
  • Page 12 – Introduction; Purpose of the Peripheral; The EMAC/MDIO has the following features:
  • Page 13 – Functional Block Diagram; Figure 1; Figure 1. EMAC and MDIO Block Diagram
  • Page 14 – Industry Standard(s) Compliance Statement; Architecture; Clock Control; Media Independent Interface (MII) Connections; Figure 2
  • Page 15 – Table 1; Figure 2. Ethernet Configuration—MII Connections
  • Page 16 – Reduced Media Independent Interface (RMII) Connections; Figure 3; Figure 3. Ethernet Configuration—RMII Connections
  • Page 17 – Ethernet Protocol Overview; Ethernet Frame Format; Figure 4; Figure 4. Ethernet Frame Format
  • Page 18 – Ethernet’s Multiple Access Protocol; Programming Interface; Packet Buffer Descriptors; Figure 5; Figure 5. Basic Descriptor Format
  • Page 19 – Table 4. Basic Descriptor Description; Figure 6. Typical Descriptor Linked List
  • Page 20 – Transmit and Receive Descriptor Queues; TXnHDP - Transmit Channel n DMA Head Descriptor Pointer Register
  • Page 21 – Transmit and Receive EMAC Interrupts; Figure 7
  • Page 22 – Figure 7. Transmit Buffer Descriptor Format; Example 1. Transmit Buffer Descriptor in C Structure Format
  • Page 23 – Next Descriptor Pointer
  • Page 25 – Receive Buffer Descriptor Format; Figure 8; Figure 8. Receive Buffer Descriptor Format
  • Page 26 – Example 2. Receive Buffer Descriptor in C Structure Format; Buffer Offset
  • Page 27 – Buffer Length
  • Page 29 – EMAC Control Module; The EMAC control module (; Figure 9. EMAC Control Module Block Diagram
  • Page 30 – Interrupt Control; MDIO Module; MDIO Module Components; MDIO clock generator
  • Page 31 – Figure 10. MDIO Module Block Diagram; MDIO Clock Generator
  • Page 32 – MDIO Module Operational Overview
  • Page 33 – Initializing the MDIO Module
  • Page 34 – Example of MDIO Register Access Code; Example 3
  • Page 35 – EMAC Module; EMAC Module Components; Statistics logic; Figure 11. EMAC Module Block Diagram; Receive DMA Engine
  • Page 36 – EMAC Module Operational Overview
  • Page 37 – MAC Interface; Data Reception; Receive Control
  • Page 38 – Collision-Based Receive Buffer Flow Control
  • Page 39 – Data Transmission; Transmit Control
  • Page 40 – Transmit Flow Control
  • Page 41 – Packet Receive Operation; Receive DMA Host Configuration; To configure the receive DMA for operation the host must:; Receive Channel Enabling
  • Page 42 – Hardware Receive QOS Support
  • Page 43 – Receive Frame Classification; Table 5
  • Page 44 – Table 5. Receive Frame Treatment Summary
  • Page 45 – Receive Overrun; The types of receive overrun are:; Table 6. Middle of Frame Overrun Treatment
  • Page 46 – Packet Transmit Operation; Transmit DMA Host Configuration; To configure the transmit DMA for operation the host must perform:; Transmit Channel Teardown; Any frame currently in transmission completes normally.
  • Page 47 – Receive and Transmit Latency; s in 10 Mbps mode. The memory; Transfer Node Priority
  • Page 48 – Reset Considerations; Software Reset Considerations
  • Page 49 – Enabling the EMAC/MDIO Peripheral; Initializing the EMAC and MDIO modules; MDIO Module Initialization; s to read one register, it can be
  • Page 50 – EMAC Module Initialization; TXEN bit in TXCONTROL. Then set the GMIIEN bit in MACCONTROL.
  • Page 51 – Interrupt Support; EMAC Module Interrupt Events and Requests; STATPEND: Statistics interrupt
  • Page 52 – Statistics Interrupt
  • Page 53 – Ownership bit not set in input buffer; MDIO Module Interrupt Events and Requests; Link Change Interrupt
  • Page 54 – User Access Completion Interrupt; Proper Interrupt Processing; for; Interrupt Multiplexing
  • Page 55 – Power Management; Table 7; Emulation suspend has not been tested.; Table 7. Emulation Control
  • Page 56 – EMAC Control Module Registers; Table 8; Table 8. EMAC Control Module Registers
  • Page 57 – EMAC Control Module Revision ID Register (REVID); The EMAC control module revision ID register (REVID) is shown in
  • Page 58 – EMAC Control Module Software Reset Register (SOFTRESET); and described; Figure 13. EMAC Control Module Software Reset Register (SOFTRESET)
  • Page 59 – EMAC Control Module Interrupt Control Register (INTCONTROL)
  • Page 60 – and described in
  • Page 70 – MDIO Registers; for the memory address of these registers.; Table 23. MDIO Revision ID Register (REVID) Field Descriptions
  • Page 71 – The MDIO control register (CONTROL) is shown in
  • Page 72 – The PHY acknowledge status register (ALIVE) is shown in; The PHY link status register (LINK) is shown in
  • Page 73 – and; Field Descriptions
  • Page 78 – MDIO User Command Complete Interrupt Mask Clear Register
  • Page 79 – The MDIO user access register 0 (USERACCESS0) is shown in
  • Page 80 – The MDIO user PHY select register 0 (USERPHYSEL0) is shown in
  • Page 81 – The MDIO user access register 1 (USERACCESS1) is shown in
  • Page 82 – The MDIO user PHY select register 1 (USERPHYSEL1) is shown in
  • Page 83 – EMAC Module Registers; memory address of these registers.
  • Page 86 – The transmit revision ID register (TXREVID) is shown in
  • Page 87 – The transmit teardown register (TXTEARDOWN) is shown in
  • Page 88 – The receive revision ID register (RXREVID) is shown in; Table 42. Receive Control Register (RXCONTROL) Field Descriptions
  • Page 89 – The receive teardown register (RXTEARDOWN) is shown in
  • Page 92 – Transmit Interrupt Mask Set Register (TXINTMASKSET); Figure 47. Transmit Interrupt Mask Set Register (TXINTMASKSET)
  • Page 94 – The MAC input vector register (MACINVECTOR) is shown in
  • Page 95 – The MAC end of interrupt vector register (MACEOIVECTOR) is shown in; Figure 50. MAC End Of Interrupt Vector Register (MACEOIVECTOR)
  • Page 98 – The receive interrupt mask set register (RXINTMASKSET) is shown in; Figure 53. Receive Interrupt Mask Set Register (RXINTMASKSET)
  • Page 99 – Figure 54. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
  • Page 101 – The MAC interrupt mask set register (MACINTMASKSET) is shown in; Figure 58. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
  • Page 105 – The receive unicast enable set register (RXUNICASTSET) is shown in; Figure 60. Receive Unicast Enable Set Register (RXUNICASTSET)
  • Page 106 – The receive unicast clear register (RXUNICASTCLEAR) is shown in
  • Page 107 – The receive maximum length register (RXMAXLEN) is shown in
  • Page 108 – Receive Channel Flow Control Threshold Registers
  • Page 110 – The MAC control register (MACCONTROL) is shown in; Table 66. MAC Control Register (MACCONTROL) Field Descriptions
  • Page 112 – The MAC status register (MACSTATUS) is shown in
  • Page 114 – The emulation control register (EMCONTROL) is shown in; Table 69. FIFO Control Register (FIFOCONTROL) Field Descriptions
  • Page 115 – The MAC configuration register (MACCONFIG) is shown in
  • Page 116 – Figure 73. MAC Source Address Low Bytes Register (MACSRCADDRLO); Figure 74. MAC Source Address High Bytes Register (MACSRCADDRHI)
  • Page 117 – The MAC hash address register 1 (MACHASH1) is shown in; Table 74. MAC Hash Address Register 1 (MACHASH1) Field Descriptions; The MAC hash address register 2 (MACHASH2) is shown in
  • Page 118 – The back off test register (BOFFTEST) is shown in; Table 76. Back Off Test Register (BOFFTEST) Field Descriptions; Figure 78. Transmit Pacing Algorithm Test Register (TPACETEST)
  • Page 119 – The receive pause timer register (RXPAUSE) is shown in
  • Page 121 – The MAC address high bytes register (MACADDRHI) is shown in
  • Page 124 – Network Statistics Registers; Figure 88. Statistics Register; Good Receive Frames Register (RXGOODFRAMES)
  • Page 125 – Pause Receive Frames Register (RXPAUSEFRAMES)
  • Page 126 – Receive Oversized Frames Register (RXOVERSIZED)
  • Page 130 – Was any size
  • Page 131 – Also counted in this statistic is:
  • Page 133 – Appendix A Glossary; Device — In this document, device refers to the processor.; of a single Ethernet frame on the wire.
  • Page 134 – Appendix A; Table 87. Physical Layer Definitions; Port— Ethernet device.
  • Page 135 – Appendix B Revision History; Table 88. Document Revision History
  • Page 136 – IMPORTANT NOTICE
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TMS320C674x/OMAP-L1x Processor
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO) Module

User's Guide

Literature Number: SPRUFL5B

April 2011

"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.

Summary

Page 10 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; SPRUGM5

Preface SPRUFL5B – April 2011 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device.Included are the features of the EMAC and ...

Page 11 - SPRUGM7

www.ti.com Related Documentation From Texas Instruments SPRUGM7 — OMAP-L138 Applications Processor System Reference Guide. Describes the System-on-Chip (SoC) including the ARM subsystem, DSP subsystem, system memory, deviceclocking, phase-locked loop controller (PLLC), power and sleep controller (PS...

Page 12 - Introduction; Purpose of the Peripheral; The EMAC/MDIO has the following features:

User's Guide SPRUFL5B – April 2011 EMAC/MDIO Module 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device.Included are the features of the EMAC a...

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