Texas Instruments TMS320DM36X - Manual

Texas Instruments TMS320DM36X

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Table of Contents:

  • Page 4 – Ethernet Media Access Controller (EMAC) Registers
  • Page 10 – Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; SPRUFG5
  • Page 13 – Introduction; Purpose of the Peripheral
  • Page 14 – Emulation support; Functional Block Diagram; Figure 1. EMAC and MDIO Block Diagram; Figure 1
  • Page 15 – for details of interrupt multiplex logic of the EMAC control; Industry Standard(s) Compliance Statement; Architecture; Clock Control; MII Clocking
  • Page 16 – Memory Map; Media Independent Interface (MII) Connections; Figure 2; Figure 2. Ethernet Configuration MII Connections
  • Page 17 – Table 1. EMAC and MDIO Signals for MII Interface; Pin Multiplexing
  • Page 18 – Ethernet Protocol Overview; Ethernet Frame Format; Figure 3; Figure 3. Ethernet Frame Format
  • Page 19 – Ethernet’s Multiple Access Protocol; the frame in a buffer.; Programming Interface; Packet Buffer Descriptors; Figure 4; Figure 4. Basic Descriptor Format
  • Page 20 – Table 3. Basic Descriptor Description; Figure 5. Typical Descriptor Linked List
  • Page 21 – Transmit and Receive Descriptor Queues; TXnHDP - Transmit Channel n DMA Head Descriptor Pointer Register
  • Page 22 – Transmit and Receive EMAC Interrupts; , using the linked list
  • Page 23 – Transmit Buffer Descriptor Format; Figure 6; Figure 6. Transmit Buffer Descriptor Format; Example 1. Transmit Buffer Descriptor in C Structure Format
  • Page 24 – Next Descriptor Pointer
  • Page 26 – Receive Buffer Descriptor Format; Figure 7; Figure 7. Receive Buffer Descriptor Format
  • Page 27 – Example 2. Receive Buffer Descriptor in C Structure Format; Buffer Offset
  • Page 28 – Buffer Length
  • Page 30 – EMAC Control Module; The basic functions of the EMAC control module (; Figure 8. EMAC Control Module Block Diagram
  • Page 31 – Interrupt Control; Transmit Pulse Interrupt
  • Page 32 – Receive Threshold Pulse Interrupt; Interrupt Pacing; s pulse that is created from a
  • Page 33 – MDIO Module; MDIO Module Components; Figure 9; Figure 9. MDIO Module Block Diagram; MDIO Clock Generator
  • Page 34 – Active PHY Monitoring; MDIO Module Operational Overview
  • Page 35 – Initializing the MDIO Module
  • Page 36 – Example of MDIO Register Access Code; Example 3
  • Page 37 – EMAC Module; EMAC Module Components; Statistics logic; Figure 10. EMAC Module Block Diagram; Receive DMA Engine
  • Page 39 – EMAC Module Operational Overview
  • Page 40 – Data Reception; Receive Control
  • Page 41 – Collision-Based Receive Buffer Flow Control
  • Page 42 – Data Transmission; Transmit Control
  • Page 43 – Transmit Flow Control
  • Page 44 – Packet Receive Operation; Receive DMA Host Configuration; To configure the receive DMA for operation the host must:; Receive Channel Enabling
  • Page 45 – Receive Address Matching
  • Page 46 – Host Free Buffer Tracking; Any current frame in reception completes normally.; Receive Frame Classification
  • Page 47 – Promiscuous Receive Mode; Table 4; Table 4. Receive Frame Treatment Summary
  • Page 48 – Receive Overrun; The types of receive overrun are:; Table 5. Middle of Frame Overrun Treatment
  • Page 49 – Packet Transmit Operation; Transmit DMA Host Configuration; To configure the transmit DMA for operation the host must perform:; Transmit Channel Teardown; Any frame currently in transmission completes normally.; Receive and Transmit Latency
  • Page 50 – Transfer Node Priority; Software Reset Considerations
  • Page 51 – Hardware Reset Considerations; Initializing the EMAC and MDIO modules.
  • Page 52 – Example 4. EMAC Control Module Initialization Code
  • Page 53 – MDIO Module Initialization; Example 5
  • Page 54 – EMAC Module Initialization; TXEN bit in TXCONTROL. Then set the MIIEN bit in MACCONTROL.
  • Page 55 – Interrupt Support; EMAC Module Interrupt Events and Requests; STATPEND: Statistics interrupt; Figure 11. EMAC Control Module Interrupt Logic Diagram; Receive Threshold Interrupts
  • Page 56 – Receive Packet Completion Interrupts
  • Page 57 – Statistics Interrupt
  • Page 58 – MDIO Module Interrupt Events and Requests; USERINT: Serial interface user command event complete interrupt; Proper Interrupt Processing
  • Page 59 – Power Management; Emulation Considerations; Table 6; Table 6. Emulation Control
  • Page 60 – EMAC Control Module Registers; Table 7; Table 7. EMAC Control Module Registers; The identification and version register (CMIDVER) is shown in; Field Descriptions
  • Page 61 – EMAC Control Module Software Reset Register (CMSOFTRESET); The software reset register (CMSOFTRESET) is shown in; EMAC Control Module Emulation Control Register (CMEMCONTROL); The emulation control register (CMEMCONTROL) is shown in
  • Page 62 – EMAC Control Module Interrupt Control Register (CMINTCTRL); The interrupt control register (CMINTCTRL) is shown in
  • Page 63 – and
  • Page 64 – The transmit interrupt enable register (CMTXINTEN) is shown in
  • Page 65 – and described in
  • Page 67 – The transmit interrupt status register (CMTXINTSTAT) is shown in
  • Page 70 – MDIO Registers; for the memory address of these registers.
  • Page 71 – The MDIO control register (CONTROL) is shown in
  • Page 72 – The PHY acknowledge status register (ALIVE) is shown in
  • Page 78 – MDIO User Command Complete Interrupt Mask Clear Register
  • Page 79 – The MDIO user access register 0 (USERACCESS0) is shown in
  • Page 80 – The MDIO user PHY select register 0 (USERPHYSEL0) is shown in
  • Page 81 – The MDIO user access register 1 (USERACCESS1) is shown in
  • Page 82 – The MDIO user PHY select register 1 (USERPHYSEL1) is shown in
  • Page 83 – memory address of these registers.
  • Page 86 – Transmit Identification and Version Register (TXIDVER); Figure 40. Transmit Identification and Version Register (TXIDVER); The transmit control register (TXCONTROL) is shown in
  • Page 87 – The transmit teardown register (TXTEARDOWN) is shown in
  • Page 88 – Receive Identification and Version Register (RXIDVER); Figure 43. Receive Identification and Version Register (RXIDVER)
  • Page 89 – The receive control register (RXCONTROL) is shown in; Table 42. Receive Control Register (RXCONTROL) Field Descriptions; The receive teardown register (RXTEARDOWN) is shown in
  • Page 92 – Transmit Interrupt Mask Set Register (TXINTMASKSET); Figure 48. Transmit Interrupt Mask Set Register (TXINTMASKSET)
  • Page 94 – The MAC input vector register (MACINVECTOR) is shown in; Figure 51. MAC End Of Interrupt Vector Register (MACEOIVECTOR)
  • Page 97 – The receive interrupt mask set register (RXINTMASKSET) is shown in; Figure 54. Receive Interrupt Mask Set Register (RXINTMASKSET)
  • Page 98 – Figure 55. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
  • Page 100 – The MAC interrupt mask set register (MACINTMASKSET) is shown in; Figure 59. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
  • Page 104 – The receive unicast enable set register (RXUNICASTSET) is shown in; Figure 61. Receive Unicast Enable Set Register (RXUNICASTSET)
  • Page 105 – The receive unicast clear register (RXUNICASTCLEAR) is shown in
  • Page 106 – The receive maximum length register (RXMAXLEN) is shown in
  • Page 109 – The MAC control register (MACCONTROL) is shown in; Table 66. MAC Control Register (MACCONTROL) Field Descriptions
  • Page 111 – The MAC status register (MACSTATUS) is shown in
  • Page 113 – The emulation control register (EMCONTROL) is shown in; Table 69. FIFO Control Register (FIFOCONTROL) Field Descriptions
  • Page 114 – The MAC configuration register (MACCONFIG) is shown in
  • Page 115 – Figure 74. MAC Source Address Low Bytes Register (MACSRCADDRLO); and described; Figure 75. MAC Source Address High Bytes Register (MACSRCADDRHI)
  • Page 116 – The MAC hash address register 1 (MACHASH1) is shown in; Table 74. MAC Hash Address Register 1 (MACHASH1) Field Descriptions; The MAC hash address register 2 (MACHASH2) is shown in; Table 75. MAC Hash Address Register 2 (MACHASH2) Field Descriptions
  • Page 117 – The back off test register (BOFFTEST) is shown in; Table 76. Back Off Test Register (BOFFTEST) Field Descriptions; Figure 79. Transmit Pacing Algorithm Test Register (TPACETEST)
  • Page 118 – The receive pause timer register (RXPAUSE) is shown in
  • Page 120 – The MAC address high bytes register (MACADDRHI) is shown in
  • Page 123 – Network Statistics Registers; Figure 89. Statistics Register; Good Receive Frames Register (RXGOODFRAMES)
  • Page 124 – Pause Receive Frames Register (RXPAUSEFRAMES)
  • Page 125 – Receive Jabber Frames Register (RXJABBER)
  • Page 130 – Also counted in this statistic is:
  • Page 131 – Appendix A Glossary; portion of a single Ethernet frame on the wire.
  • Page 132 – Appendix A; Table 87. Physical Layer Definitions; Port— Ethernet device.
  • Page 133 – Appendix B Revision History; Table 88. Document Revision History
  • Page 134 – IMPORTANT NOTICE
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TMS320DM36x Digital Media System-on-Chip
(DMSoC)
Ethernet Media Access Controller (EMAC)

User's Guide

Literature Number: SPRUFI5B

March 2009 – Revised December 2010

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Summary

Page 4 - Ethernet Media Access Controller (EMAC) Registers

www.ti.com 4.1 MDIO Version Register (VERSION) ................................................................................. 70 4.2 MDIO Control Register (CONTROL) ................................................................................ 71 4.3 PHY Acknowledge Status Register (ALIVE) .......

Page 10 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; SPRUFG5

Preface SPRUFI5B – March 2009 – Revised December 2010 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Management Data Input/Output (MDIO) module integrated in theTMS320DM36x Digital Media ...

Page 13 - Introduction; Purpose of the Peripheral

User's Guide SPRUFI5B – March 2009 – Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Management Data Input/Ou...

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