Texas Instruments TMS320DM643x DMP - Manual

Texas Instruments TMS320DM643x DMP

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Table of Contents:

  • Page 3 – Contents
  • Page 10 – Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; . Tip: Enter the literature number in the search box
  • Page 11 – Introduction; Purpose of the Peripheral; The EMAC/MDIO has the following features:
  • Page 12 – Functional Block Diagram; Figure 1; Figure 1. EMAC and MDIO Block Diagram
  • Page 13 – Industry Standard(s) Compliance Statement; Clock Control; Peripheral Architecture; 2 bits in size. Data can be written to and
  • Page 14 – Figure 2. Typical Ethernet Configuration
  • Page 15 – Ethernet Protocol Overview; Ethernet Frame Format; Figure 3; Figure 3. Ethernet Frame Format
  • Page 16 – Ethernet’s Multiple Access Protocol; Programming Interface; Packet Buffer Descriptors; the frame in a buffer.; Figure 4. Basic Descriptor Format
  • Page 17 – Table 3. Basic Descriptor Description; Figure 5. Typical Descriptor Linked List
  • Page 18 – Transmit and Receive Descriptor Queues; TXnHDP - Transmit Channel n DMA Head Descriptor Pointer Register
  • Page 19 – Transmit and Receive EMAC Interrupts; , using the linked list
  • Page 20 – Transmit Buffer Descriptor Format; Figure 6; Figure 6. Transmit Buffer Descriptor Format; Example 1. Transmit Buffer Descriptor in C Structure Format
  • Page 21 – The range of legal values for this field is 0 to (Buffer Length – 1).
  • Page 23 – Receive Buffer Descriptor Format; Next Descriptor Pointer; Figure 7; Figure 7. Receive Buffer Descriptor Format
  • Page 24 – Buffer Offset; Example 2. Receive Buffer Descriptor in C Structure Format
  • Page 25 – This 16-bit field is used for two purposes:
  • Page 27 – EMAC Control Module; Internal Memory; The basic functions of the EMAC control module (; Figure 8. EMAC Control Module Block Diagram
  • Page 28 – Interrupt Control; MDIO Module; MDIO Module Components; Figure 9
  • Page 29 – Figure 9. MDIO Module Block Diagram
  • Page 30 – MDIO Module Operational Overview
  • Page 31 – PHY and PHY register you want to write.
  • Page 32 – Example of MDIO Register Access Code; Start the process of reading a PHY register
  • Page 33 – EMAC Module; EMAC Module Components; Receive DMA Engine; Statistics logic; Figure 10. EMAC Module Block Diagram
  • Page 34 – EMAC Module Operational Overview
  • Page 35 – Data Reception; Receive Control; Collision-based flow control for half-duplex mode
  • Page 36 – Collision-Based Receive Buffer Flow Control; The EMAC transmits pause frames as described below:
  • Page 37 – Data Transmission; Transmit Control
  • Page 38 – Transmit Flow Control
  • Page 39 – Packet Receive Operation; Receive DMA Host Configuration; To configure the receive DMA for operation the host must:
  • Page 41 – Table 4
  • Page 42 – Table 4. Receive Frame Treatment Summary
  • Page 43 – Receive Overrun; The types of receive overrun are:; Table 5. Middle of Frame Overrun Treatment
  • Page 44 – Packet Transmit Operation; Transmit DMA Host Configuration; Receive and Transmit Latency
  • Page 45 – Software Reset Considerations; PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (
  • Page 46 – Initializing the EMAC and MDIO modules.
  • Page 47 – MDIO Module Initialization; Example 4. EMAC Control Module Initialization Code; Example 5
  • Page 48 – EMAC Module Initialization; TXEN bit in TXCONTROL. Then set the GMIIEN bit in MACCONTROL.
  • Page 49 – Interrupt Support; EMAC Module Interrupt Events and Requests; Transmit Packet Completion Interrupts; The EMAC module generates 18 interrupt events:
  • Page 51 – MDIO Module Interrupt Events and Requests; Link Change Interrupt; Proper Interrupt Processing; The MDIO module generates two interrupt events:
  • Page 52 – Table 6; Emulation suspend has not been tested.; Table 6. Emulation Control
  • Page 53 – EMAC Control Module Interrupt Control Register (EWCTL); EMAC Control Module Registers; Table 7; Table 7. EMAC Control Module Registers; The EWCTL is shown in; Figure 11. EMAC Control Module Interrupt Control Register (EWCTL)
  • Page 54 – EMAC Control Module Interrupt Timer Count Register (EWINTTCNT); The EWINTTCNT is shown in
  • Page 55 – MDIO Registers; for the memory address of these registers.
  • Page 56 – The MDIO control register (CONTROL) is shown in
  • Page 57 – The PHY acknowledge status register (ALIVE) is shown in
  • Page 58 – and; Field Descriptions
  • Page 60 – and described in
  • Page 64 – The MDIO user access register 0 (USERACCESS0) is shown in
  • Page 65 – The MDIO user PHY select register 0 (USERPHYSEL0) is shown in
  • Page 66 – The MDIO user access register 1 (USERACCESS1) is shown in
  • Page 67 – The MDIO user PHY select register 1 (USERPHYSEL1) is shown in
  • Page 68 – Ethernet Media Access Controller (EMAC) Registers; memory address of these registers.
  • Page 71 – Transmit Identification and Version Register (TXIDVER); Figure 27. Transmit Identification and Version Register (TXIDVER); The transmit control register (TXCONTROL) is shown in
  • Page 72 – The transmit teardown register (TXTEARDOWN) is shown in
  • Page 73 – Receive Identification and Version Register (RXIDVER); Figure 30. Receive Identification and Version Register (RXIDVER); The receive control register (RXCONTROL) is shown in; Table 30. Receive Control Register (RXCONTROL) Field Descriptions
  • Page 74 – The receive teardown register (RXTEARDOWN) is shown in
  • Page 77 – Transmit Interrupt Mask Set Register (TXINTMASKSET); Figure 35. Transmit Interrupt Mask Set Register (TXINTMASKSET)
  • Page 79 – The MAC input vector register (MACINVECTOR) is shown in
  • Page 82 – The receive interrupt mask set register (RXINTMASKSET) is shown in; Figure 40. Receive Interrupt Mask Set Register (RXINTMASKSET)
  • Page 83 – Figure 41. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
  • Page 85 – The MAC interrupt mask set register (MACINTMASKSET) is shown in; Figure 45. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
  • Page 89 – The receive unicast enable set register (RXUNICASTSET) is shown in; Figure 47. Receive Unicast Enable Set Register (RXUNICASTSET)
  • Page 90 – The receive unicast clear register (RXUNICASTCLEAR) is shown in
  • Page 91 – The receive maximum length register (RXMAXLEN) is shown in
  • Page 94 – The MAC control register (MACCONTROL) is shown in; Table 53. MAC Control Register (MACCONTROL) Field Descriptions
  • Page 96 – The MAC status register (MACSTATUS) is shown in
  • Page 98 – The emulation control register (EMCONTROL) is shown in; Table 56. FIFO Control Register (FIFOCONTROL) Field Descriptions
  • Page 99 – The MAC configuration register (MACCONFIG) is shown in
  • Page 100 – Figure 60. MAC Source Address Low Bytes Register (MACSRCADDRLO); and described; Figure 61. MAC Source Address High Bytes Register (MACSRCADDRHI)
  • Page 101 – The MAC hash address register 1 (MACHASH1) is shown in; Table 61. MAC Hash Address Register 1 (MACHASH1) Field Descriptions; The MAC hash address register 2 (MACHASH2) is shown in; Table 62. MAC Hash Address Register 2 (MACHASH2) Field Descriptions
  • Page 102 – The back off test register (BOFFTEST) is shown in; Table 63. Back Off Test Register (BOFFTEST) Field Descriptions; Figure 65. Transmit Pacing Algorithm Test Register (TPACETEST)
  • Page 103 – The receive pause timer register (RXPAUSE) is shown in
  • Page 105 – The MAC index register (MACINDEX) is shown in
  • Page 108 – Network Statistics Registers; Good Receive Frames Register (RXGOODFRAMES); Figure 75. Statistics Register
  • Page 114 – Was any size
  • Page 115 – Also counted in this statistic is:
  • Page 117 – Appendix A Glossary; portion of a single Ethernet frame on the wire.
  • Page 118 – Appendix A; Port — Ethernet device.
  • Page 119 – Appendix B Revision History
  • Page 120 – IMPORTANT NOTICE
Loading the manual

TMS320DM643x DMP

Ethernet Media Access Controller (EMAC)/

Management Data Input/Output (MDIO)

Module

User's Guide

Literature Number: SPRU941A

April 2007

"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.

Summary

Page 3 - Contents

Contents Preface .............................................................................................................................. 10 1 Introduction .............................................................................................................. 11 1.1 Purpose of the Perip...

Page 10 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; . Tip: Enter the literature number in the search box

Preface SPRU941A – April 2007 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Management Data Input/Output (MDIO) module integrated in theTMS320DM643x Digital Media Processor (DMP). Includ...

Page 11 - Introduction; Purpose of the Peripheral; The EMAC/MDIO has the following features:

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRU941A – April 2007 Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Mana...

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