Texas Instruments TMS320TCI6486 - Manual

Texas Instruments TMS320TCI6486

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Table of Contents:

  • Page 4 – EMAC Port Registers
  • Page 5 – Appendix A Glossary
  • Page 10 – Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; the TMS320C6000TM DSPs and includes application program examples.
  • Page 11 – Introduction; Purpose of the Peripheral; Little endian and big endian support.
  • Page 12 – Single MDIO, shared by both EMAC modules.; Functional Block Diagram; Figure 1; Figure 1. EMAC and MDIO Block Diagram
  • Page 13 – . The device has two serial management; Table 1. Serial Management Interface Pins; Table 2
  • Page 14 – be powered down even when the module is enabled.; Industry Standard(s) Compliance Statement
  • Page 15 – EMAC Functional Architecture; Clock Control; Table 3. EMAC Clock Specifications; MII Clocking
  • Page 16 – GMII Clocking; Memory Map
  • Page 17 – System-Level Connections; Table 4; Table 4. EMAC0 Interface Selection Pins; Table 5. EMAC1 Interface Selection Pins; Table 6
  • Page 18 – Media Independent Interface (MII) Connections; Figure 2; Figure 2. Ethernet Configuration with MII Interface; Table 7
  • Page 19 – Table 7. EMAC and MDIO Signals for MII Interface
  • Page 20 – Reduced Media Independent Interface (RMII) Connections; Figure 3; Figure 3. Ethernet Configuration with RMII Interface; Table 8; Table 8. EMAC and MDIO Signals for RMII Interface
  • Page 21 – Table 8. EMAC and MDIO Signals for RMII Interface (continued); Gigabit Media Independent Interface (GMII) Connections; Figure 4; Figure 4. Ethernet Configuration with GMII Interface; Table 9
  • Page 22 – Table 9. EMAC and MDIO Signals for GMII Interface; Reduced Gigabit Media Independent Interface (RGMII) Connections; Figure 5
  • Page 23 – Figure 5. Ethernet Configuration with RGMII Interface; MRXDV signal (multiplexed in the RGRXCTL signal) is true; Table 10. EMAC and MDIO Signals for RGMII Interface
  • Page 24 – Table 10. EMAC and MDIO Signals for RGMII Interface (continued)
  • Page 25 – Figure 6; Figure 6. Ethernet Configuration with S3MII Interface
  • Page 26 – Table 11. EMAC and MDIO Signals for S3MII Interface; Figure 7
  • Page 28 – Figure 8; Figure 8. S3MII Switch Configuration
  • Page 29 – Ethernet Protocol Overview; Ethernet Frame Format; Figure 9; Figure 9. Ethernet Frame
  • Page 30 – Multiple Access Protocol
  • Page 31 – Programming Interface; Packet Buffer Descriptors; The basic descriptor format is shown in; Figure 10. Basic Descriptor Format
  • Page 32 – Figure 11. Typical Descriptor Linked List; The EMAC module processes descriptors in linked list chains (
  • Page 33 – Transmit and Receive EMAC Interrupts; The EMAC processes descriptors in linked list chains (
  • Page 34 – Transmit Buffer Descriptor Format; ) is a contiguous block of four 32-bit data words aligned on a; Figure 12. Transmit Descriptor Format; Example 1. Transmit Descriptor in C Structure Format
  • Page 35 – Next Descriptor Pointer
  • Page 37 – Receive Buffer Descriptor Format; Figure 13. Receive Descriptor Format; Example 2. Receive Descriptor in C Structure Format
  • Page 39 – Jabber Flag
  • Page 40 – Control Flag; Communications Port Programming Interface (CPPI)
  • Page 41 – Interrupt combiner; Figure 14. EMIC Block Diagram
  • Page 42 – Pacing Block
  • Page 43 – Section 3; Figure 16. TDSM State Transition Diagram
  • Page 44 – Figure 17. DSM State Transition Diagram
  • Page 45 – Transmit Pacer and Interrupt Combiner (TPIC); Optionally implements pacing for transmit events.; Figure 18. Transmit Pacer and Interrupt Combiner
  • Page 46 – Receive Pacer and Interrupt Combiner (RPIC); Implements pacing for receive events.; Figure 19. Receive Pacer and Interrupt Combiner
  • Page 47 – Figure 20. Common Interrupt Combiner
  • Page 48 – Figure 21. MDIO Module Block Diagram; MDIO Clock Generator
  • Page 49 – MDIO Module Operational Overview; Initializing the MDIO Module
  • Page 50 – Writing Data to a PHY Register
  • Page 51 – Example 3
  • Page 52 – EMAC Module; EMAC Module Components; , the number associated with each MII interface; Figure 22. EMAC Module Block Diagram; Each EMAC peripheral used has the following components:
  • Page 53 – can be sent to only a single channel.; EMAC Module Operational Overview
  • Page 54 – Media Independent Interfaces; Data Reception; Receive Control
  • Page 55 – Collision-Based Receive Buffer Flow Control
  • Page 56 – Data Transmission; Transmit Control
  • Page 57 – Back Off
  • Page 58 – Packet Receive Operation; Receive DMA Host Configuration; Initialize the receive addresses; Receive Channel Enabling
  • Page 59 – Hardware Receive QOS Support
  • Page 60 – Receive Channel Teardown; Any current frame in reception completes normally.; Receive Frame Classification
  • Page 61 – Promiscuous Receive Mode; shows the effects of the promiscuous enable bits. Proper; Table 14. Receive Frame Treatment Summary
  • Page 62 – Receive Overrun; The types of receive overruns are:; Packet Transmit Operation; Transmit DMA Host Configuration
  • Page 63 – Initialize the TXnHDP registers to zero.; Transmit Channel Teardown; Any frame currently in transmission completes normally.; Receive and Transmit Latency
  • Page 64 – Reset Considerations; Software Reset Considerations; Fixed-Point Digital Signal Processor data manual (; Hardware Reset Considerations
  • Page 65 – Enabling the EMAC/MDIO Peripheral; TMS320C6472 Fixed-Point Digital Signal Processor data manual (; EMIC Module Initialization; Example 4
  • Page 66 – s to read one register, the MDIO; EMAC Module Initialization; contained in the CPPI buffer manager.
  • Page 67 – Interrupt Support; EMAC Module Interrupt Events and Requests; STATPEND: Statistics interrupt
  • Page 68 – Statistics Interrupt; MDIO Module Interrupt Events and Requests
  • Page 69 – Link Change Interrupt; Proper Interrupt Processing; Power Management; ) or the TMS320C6472 Fixed-Point Digital Signal Processor data; Emulation Considerations
  • Page 70 – Table 16. Emulation Control
  • Page 71 – EMIC Module Registers; RPIC Registers; RPCFG Registers
  • Page 72 – Figure 24. RPCFG Register
  • Page 73 – RPSTAT Registers; and described in; Figure 25. RPSTAT Register
  • Page 74 – TPIC Registers; TPCFG Registers; Figure 26. TPCFG Register
  • Page 75 – TPSTAT Registers; Figure 27. TPSTAT Register
  • Page 76 – MDIO Registers
  • Page 77 – The MDIO version register (VERSION) is shown in
  • Page 78 – The MDIO control register (CONTROL) is shown in
  • Page 79 – The PHY acknowledge status register (ALIVE) is shown in
  • Page 80 – The PHY link status register (LINK) is shown in
  • Page 81 – and; Descriptions
  • Page 86 – MDIO User Command Complete Interrupt Mask Clear Register; Field Descriptions
  • Page 87 – The MDIO user access register 0 (USERACCESS0) is shown in
  • Page 88 – The MDIO user PHY select register 0 (USERPHYSEL0) is shown in
  • Page 89 – The MDIO user access register 1 (USERACCESS1) is shown in
  • Page 90 – The MDIO user PHY select register 1 (USERPHYSEL1) is shown in
  • Page 95 – Transmit Identification and Version Register (TXIDVER); Figure 43. Transmit Identification and Version Register (TXIDVER)
  • Page 96 – The transmit control register (TXCONTROL) is shown in
  • Page 97 – The transmit teardown register (TXTEARDOWN) is shown in
  • Page 98 – Receive Identification and Version Register (RXIDVER); Figure 46. Receive Identification and Version Register (RXIDVER)
  • Page 99 – The receive control register (RXCONTROL) is shown in; Table 41. Receive Control Register (RXCONTROL) Field Descriptions
  • Page 100 – The receive teardown register (RXTEARDOWN) is shown in
  • Page 101 – and described
  • Page 103 – Transmit Interrupt Mask Set Register (TXINTMASKSET); Figure 51. Transmit Interrupt Mask Set Register (TXINTMASKSET)
  • Page 105 – The MAC input vector register (MACINVECTOR) is shown in
  • Page 109 – The receive interrupt mask set register (RXINTMASKSET) is shown in; Figure 57. Receive Interrupt Mask Set Register (RXINTMASKSET)
  • Page 110 – Figure 58. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
  • Page 113 – The MAC interrupt mask set register (MACINTMASKSET) is shown in
  • Page 114 – Figure 62. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
  • Page 118 – The receive unicast enable set register (RXUNICASTSET) is shown in; Figure 64. Receive Unicast Enable Set Register (RXUNICASTSET)
  • Page 119 – The receive unicast clear register (RXUNICASTCLEAR) is shown in
  • Page 120 – The receive maximum length register (RXMAXLEN) is shown in
  • Page 121 – The receive buffer offset register (RXBUFFEROFFSET) is shown in
  • Page 125 – The MAC control register (MACCONTROL) is shown in; Table 65. MAC Control Register (MACCONTROL) Field Descriptions
  • Page 127 – The MAC status register (MACSTATUS) is shown in
  • Page 129 – The emulation control register (EMCONTROL) is shown in
  • Page 130 – The FIFO control register (FIFOCONTROL) is shown in; Table 68. FIFO Control Register (FIFOCONTROL) Field Descriptions
  • Page 131 – The MAC configuration register (MACCONFIG) is shown in
  • Page 132 – The soft reset register (SOFTRESET) is shown in
  • Page 133 – Figure 77. MAC Source Address Low Bytes Register (MACSRCADDRLO)
  • Page 134 – Figure 78. MAC Source Address High Bytes Register (MACSRCADDRHI)
  • Page 135 – The MAC hash address register 1 (MACHASH1) is shown in; Table 73. MAC Hash Address Register 1 (MACHASH1) Field Descriptions
  • Page 136 – The MAC hash address register 2 (MACHASH2) is shown in; Table 74. MAC Hash Address Register 2 (MACHASH2) Field Descriptions
  • Page 137 – The back off test register (BOFFTEST) is shown in; Table 75. Back Off Test Register (BOFFTEST) Field Descriptions
  • Page 138 – Figure 82. Transmit Pacing Algorithm Test Register (TPACETEST)
  • Page 139 – The receive pause timer register (RXPAUSE) is shown in
  • Page 140 – The transmit pause timer register (TXPAUSE) is shown in
  • Page 141 – The MAC address low bytes register (MACADDRLO) is shown in
  • Page 142 – The MAC address high bytes register (MACADDRHI) is shown in
  • Page 143 – The MAC index register (MACINDEX) is shown in
  • Page 148 – Network Statistics Registers; Figure 92. Statistics Register; Table 86. Statistics Register Field Descriptions; Good Receive Frames Register (RXGOODFRAMES)
  • Page 149 – Multicast Receive Frames Register (RXMCASTFRAMES)
  • Page 150 – Receive Oversized Frames Register (RXOVERSIZED)
  • Page 154 – Was any size
  • Page 155 – Also counted in this statistic is:
  • Page 157 – of a single Ethernet frame on the wire.
  • Page 158 – Appendix A; Term; Twisted pair; Port— Ethernet device.
  • Page 159 – Appendix B Revision History
  • Page 160 – IMPORTANT NOTICE
Loading the manual

TMS320C6472/TMS320TCI6486 DSP
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO) Module

User's Guide

Literature Number: SPRUEF8F

March 2006 – Revised November 2010

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Summary

Page 4 - EMAC Port Registers

www.ti.com 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ................. 86 4.12 MDIO User Access Register 0 (USERACCESS0) ................................................................ 87 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) ........................

Page 5 - Appendix A Glossary

www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) ............................................................. 141 5.44 MAC Address High Bytes Register (MACADDRHI) ............................................................. 142 5.45 MAC Index Register (MACINDEX) ............................

Page 10 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; the TMS320C6000TM DSPs and includes application program examples.

Preface SPRUEF8F – March 2006 – Revised November 2010 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) andPhysical layer (PHY) device Management Data Input/Output (MDIO) module integrated withTMS320TCI6486/TMS320C6472 de...

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