Page 3 - Preface
Contents Preface ....................................................................................................................................... 9 1 System Control ................................................................................................................. 13 1.1 Introdu...
Page 9 - About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; functional exceptions to the CPU behavior.; SPRUFO1A
Preface SPRUFX5A – October 2010 – Revised November 2010 Read This First About This Manual This document describes various aspects of the TMS320C5515 digital signal processor (DSP) including:system memory, device clocking options and operation of the DSP clock generator, power managementfeatures, int...
Page 11 - SPRUGH5
www.ti.com Related Documentation From Texas Instruments SPRUGH5 — TMS320C5505 DSP System User's Guide. This document describes various aspects of the TMS320C5505 digital signal processor (DSP) including: system memory, device clockingoptions and operation of the DSP clock generator, power management...
Page 13 - Chapter 1; Introduction; A C55x CPU and associated memory
PLL/Clock Generator Power Management Pin Multiplexing JTAG Interface 64 KB DARAM 256 KB SARAM 128 KB ROM Switched Central Resource (SCR) Input Clock(s) FFT Hardware Accelerator C55x™ DSP CPU DSP System LCD Bridge Display I S (x4) 2 I C 2 SPI UART Serial Interfaces 10-Bit SAR ADC App-Spec USB 2.0 PHY...
Page 14 - Tightly coupled to the CPU are the following components:; Using FFT Accelerator ROM routines; Address
Introduction www.ti.com 1.1.2 CPU Core The C55x CPU is responsible for performing the digital signal processing tasks required by theapplication. In addition, the CPU acts as the overall system controller, responsible for handling manysystem functions such as system-level initialization, configurati...
Page 15 - SPRABB6
www.ti.com Introduction Note that for the FFT routines, output data is dependent on the return value (T0). If return = 0 output datais in-place, meaning the result will overwrite the input buffer. If return =1, output data is placed in thescratch buffer. The 32-bit input and output data consist of 1...
Page 16 - System Memory
System Memory www.ti.com modes. • Three 32-bit timers with 16-bit prescaler; one timer supports watchdog functionality. • A USB 2.0 slave. • A 10-bit successive approximation (SAR) analog-to-digital converter with touchscreen conversioncapability. • One real-time clock (RTC) with associated low powe...
Page 17 - As shown in; Memory Block
0001 0000h 64K Minus 192 Bytes DARAM (D) 0009 0000h SARAM 256K Bytes External-CS2 Space (C) 0200 0000h 0300 0000h 0400 0000h 0500 0000h 050E 0000h 128K Bytes Asynchronous (if MPNMC=1)128K Bytes ROM (if MPNMC=0) External-CS3 Space (C) External-CS4 Space (C) External-CS5 Space (C) BLOCK SIZE DMA/USB/L...
Page 18 - ). Each SARAM block can perform one access per cycle (one read or one
System Memory www.ti.com Table 1-2. DARAM Blocks (continued) Memory Block CPU Byte Address Range DMA/USB Controller Byte Address Range DARAM 6 00 C000h - 00 DFFFh 0001 C000h - 0001 DFFFh DARAM 7 00 E000h - 00 FFFFh 0001 E000h - 0001 FFFFh 1.2.1.2 On-Chip Single-Access RAM (SARAM) The SARAM is locate...
Page 19 - External Memory; SPRUGU6; Synchronous EMIF Interface
www.ti.com System Memory 1.2.1.3 On-Chip Single-Access Read-Only Memory (SAROM) The zero-wait-state ROM is located at the CPU byte address range FE 0000h - FF FFFFh. The ROM iscomposed of four 16K-word blocks, for a total of 128K-bytes of ROM. Each ROM block can perform oneaccess per cycle (one read...
Page 20 - Device Clocking
Device Clocking www.ti.com pins for the load mode register command. During the mobile SDRAM initialization, the device issues theload mode register initialization command to two different addresses that differ in only the BA0 and BA1address bits. These registers are the Extended Mode register and th...
Page 21 - ) must be powered all the time but the 32.768-KHz crystal can be; and
www.ti.com Device Clocking RTC_XO pins. RTC core (CV DDRTC ) must be powered all the time but the 32.768-KHz crystal can be disabled if CLKIN is used as the clock source for the DSP. However, when the RTC oscillator is disabled,the RTC peripheral will not operate and the RTC registers (I/O address r...
Page 23 - System Clock Generator; The system clock generator (
www.ti.com System Clock Generator 1.3.2 Clock Domains The device has many clock domains defined by individually disabled portions of the clock tree structure.Understanding the clock domains and their clock enable/disable control registers is very important formanaging power and for ensuring clocks a...
Page 24 - Multiplier and Dividers; for allowed; Table 1-5. PLL Output Frequency Configuration; RDBYPASS; Powering Down and Powering Up the System PLL
CLKREF Reference Divider 1 0 CGCR2[RDBYPASS] PLL LS PLLIN PLLOUT Output Divider 0 CGCR4. [OUTDIVEN] 1 0 CCR2. [SYSCLKSEL] LS SYSCLK CLKSEL 1 0 CLKIN RTC Clock LS RTC OSC RTC_XI RTC_XO 32.768 KHz RTC_CLKOUT RTC 1 ( ) M + 4 CLKREF RDRATIO + 4 ´ ( ) M + 4 1 CLKREF RDRATIO + 4 ODRATIO + 1 ´ ´ CLKREF M +...
Page 25 - for more details on the PLL_MODE of the clock generator.; CLKOUT Pin; Bit
www.ti.com System Clock Generator When the PLL is powered up (PLL_PWRDN = 0), the PLL will start its phase-locking sequence. You mustkeep the clock generator in BYPASS MODE for at least 4 mS while the phase-locking sequence isongoing. See Section 1.4.3.2 for more details on the PLL_MODE of the clock...
Page 26 - DSP Reset Conditions of the System Clock Generator; for more information on the bypass mode of; BYPASS MODE
System Clock Generator www.ti.com 1.4.2.4 DSP Reset Conditions of the System Clock Generator The following sections describe the operation of the system clock generator when the DSP is held in resetstate and the DSP is removed from its reset state. 1.4.2.4.1 Clock Generator During Reset During reset...
Page 27 - For detailed descriptions of these bits, see; Table 1-8. Output Frequency in Bypass Mode; SYSCLK Source / Frequency; PLL MODE; detailed descriptions of these bits, see; Table 1-9. Clock Generator Control Register Bits Used In PLL Mode; Register Bit
www.ti.com System Clock Generator 1.4.3.1.2 Register Bits Used in the BYPASS MODE Table 1-7 describes the bits of the clock generator control registers that are used in the BYPASS MODE. For detailed descriptions of these bits, see Section 1.4.4 . Table 1-7. Clock Generator Control Register Bits Used...
Page 28 - lists the; in
System Clock Generator www.ti.com Table 1-9. Clock Generator Control Register Bits Used In PLL Mode (continued) Register Bit Role in Bypass Mode RDRATIO Specifies the divider ratio of the reference divider. M Specify the multiplier value for the PLL. OUTDIVEN Determines whether the output divider is...
Page 29 - shows programming examples for different PLL MODE frequencies.
www.ti.com System Clock Generator Table 1-11 shows programming examples for different PLL MODE frequencies. Table 1-11. Examples of Selecting a PLL MODE Frequency, When CLK_SEL=L RDBYPASS OUTDIVEN M RDRATIO ODRATIO PLL Output Frequency 1 0 173h X X 32.768KHz x (173h+4) = 12.288 MHz 1 1 E4Ah X 2 32.7...
Page 30 - The clock generator control register 1 (CGCR1) is shown in
System Clock Generator www.ti.com 1.4.4.1 Clock Generator Control Register 1 (CGCR1) [1C20h] The clock generator control register 1 (CGCR1) is shown in Figure 1-6 and described in Table 1-13 . Figure 1-6. Clock Generator Control Register 1 (CGCR1) [1C20h] 15 14 13 12 11 8 Reserved Reserved PLL_PWRDN...
Page 31 - The clock generator control register 3 (CGCR3) is shown in
www.ti.com System Clock Generator 1.4.4.3 Clock Generator Control Register 3 (CGCR3) [1C22h] The clock generator control register 3 (CGCR3) is shown in Figure 1-8 and described in Table 1-15 . Figure 1-8. Clock Generator Control Register 3 (CGCR3) [1C22h] 15 0 INIT R/W-0806h LEGEND: R/W = Read/Write...
Page 32 - The clock configuration register 1 (CCR1) is shown in
System Clock Generator www.ti.com 1.4.4.5 Clock Configuration Register 1 (CCR1) [1C1Eh] The clock configuration register 1 (CCR1) is shown in Figure 1-10 and described in Table 1-17 . Figure 1-10. Clock Configuration Register 1 (CCR1) [1C1Eh] 15 1 0 Reserved SDCLK_EN R-0 R/W-0 LEGEND: R = Read only;...
Page 33 - Power Management; Power Management Features
www.ti.com Power Management 1.5 Power Management 1.5.1 Overview In many applications there may be specific requirements to minimize power consumption for both powersupply (and battery) and thermal considerations. There are two components to power consumption: activepower and leakage power. Active po...
Page 34 - Power Domains; As mentioned in
Power Management www.ti.com Table 1-20. DSP Power Domains Power Domains Description Real-Time Clock Power Domain This domain powers the real-time clock digital circuits and oscillator pins ( RTC_XI, (CV DDRTC ) RTC_XO). Nominal supply voltage can be 1.05 V through 1.3 V. Note: This domain must be al...
Page 35 - CPU Domain Clock Gating; In the CPU domain, there are five CPU ports.
www.ti.com Power Management There are two distinct methods of clock gating. The first uses the ICR CPU register and the CPU's IDLEinstruction. This method is used for the following domains: CPU, IPORT, DPORT, MPORT, XPORT &HWA. See Figure 1-3 for a diagram of these domains. In this method, the I...
Page 36 - describes the read/write bits of ICR, and; ignored when an emulator is connected to the JTAG port of the DSP.
Power Management www.ti.com 1.5.3.1.1 Idle Configuration Register (ICR) [0001h] and IDLE Status Register (ISTR) [0002h] Table 1-21 describes the read/write bits of ICR, and Table 1-22 describes the read-only bits of ISTR. NOTE: To prevent an emulation lock up, idle requests to these domains may be o...
Page 37 - Table 1-23. CPU Clock Domain Idle Requirements
www.ti.com Power Management Figure 1-13. Idle Status Register (ISTR) [0002h] 15 10 9 8 Reserved HWAIS IPORTIS R-0 R-0 R-0 7 6 5 4 1 0 MPORTIS XPORTIS DPORTIS Reserved CPUIS R-0 R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 1-22. Idle Status Register (ISTR) Field Descriptions Bi...
Page 38 - To Idle the Following Module/Port; idle configuration (see; Peripheral Domain Clock Gating; leakage power consumption.; . For the peripherals that do not have the request/acknowledge
Power Management www.ti.com Table 1-23. CPU Clock Domain Idle Requirements (continued) To Idle the Following Module/Port Requirements Before Going to Idle XPORT CPU CPUI must also be set. DPORT 1.5.3.1.3 Clock Configuration Process The clock configuration indicates which portions of the CPU clock do...
Page 39 - and described in
www.ti.com Power Management 1.5.3.2.1 Peripheral Clock Gating Configuration Registers (PCGCR1 and PCGCR2) [1C02 - 1C03h] The peripheral clock gating configuration registers (PCGRC1 and PCGCR2) are used to disable the clocksof the DSP peripherals. In contrast to the idle control register (ICR), these...
Page 43 - transfers through the DMA registers.; Clock Generator Domain Clock Gating; provides more information on; USB Domain Clock Gating
www.ti.com Power Management Table 1-26. Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) Field Descriptions (continued) Bit Field Value Description 1 EMFCLKSTPACK EMIF clock stop acknowledge bit. This bit is set to 1 when the EMIF has acknowledged arequest for its clock to be stopped. Th...
Page 44 - SPRUGH9
Power Management www.ti.com 1.5.3.4.1 Clock Configuration Process The clock configuration process for the USB clock domain consists of disabling the USB peripheral clockfollowed by disabling the USB on-chip oscillator. This procedure will completely shut off USB module,which does not comply with USB...
Page 45 - RTC Domain Clock Gating
www.ti.com Power Management Table 1-27. USB System Control Register (USBSCR) Field Descriptions (continued) Bit Field Value Description 13 USBVBUSDET USB VBUS detect enable. The USB VBUS pin has two comparators that monitor thevoltage level on the pin. These comparators can be disabled for power sav...
Page 47 - The RTC interrupt flag register (RTCINTFL) is shown in
www.ti.com Power Management 1.5.4.2 RTC Interrupt Flag Register (RTCINTFL) [1920h] The RTC interrupt flag register (RTCINTFL) is shown in Figure 1-19 and described in Table 1-29 . Figure 1-19. RTC Interrupt Flag Register (RTCINTFL) [1920h] 15 14 8 ALARMFL Reserved R-0 R-0 7 6 5 4 3 2 1 0 Reserved EX...
Page 48 - Internal Memory Low Power Modes; before initiating any read or write access.; summarizes the power modes for both DARAM and SARAM.; SLPZVDD; Voltage; The RAM sleep mode control register 1 (RAMSLPMDCNTLR1) is shown in
Power Management www.ti.com 1.5.4.3 Internal Memory Low Power Modes To save power, software can place on-chip memory (DARAM or SARAM) in one of two power modes:memory retention mode and active mode. These power modes are activated through the SLPZVDD andSLPZVSS bits of the RAM Sleep Mode Control Reg...
Page 51 - IDLE2 Procedure
www.ti.com Power Management 1.5.5.1 IDLE2 Procedure In this power configuration all the power domains are turned on, the RTC and clock generator domains areenabled, the CPU domain is disabled, and the DSP peripherals are disabled. When you enter this powerconfiguration all CPU and peripheral activit...
Page 52 - IDLE3 Procedure
Power Management www.ti.com 1.5.5.2 IDLE3 Procedure In this power configuration all the power domains are turned on, the CPU and clock generator domainsare disabled, and the RTC clock domain is enabled. The DSP peripherals and the USB are also disabledin this mode. When you enter this power configur...
Page 53 - Interrupts
www.ti.com Interrupts When the core voltage is increased (1.05 V to 1.3 V) clock speed is not an issue since the device canoperate faster at the higher voltage. However, when switching from 1.05 V to 1.3 V software must allowtime for the voltage transition to reach the 1.3 V range. Additionally, ext...
Page 54 - Table 1-33. IFR0 and IER0 Bit Descriptions
Interrupts www.ti.com Table 1-32. Interrupt Table (continued) SOFTWARE RELATIVE NAME (TRAP) LOCATION PRIORITY FUNCTION EQUIVALENT (HEX BYTES) (1) - SINT28 0xE0 15 Software interrupt #28 - SINT29 0xE8 16 Software interrupt #29 - SINT30 0xF0 17 Software interrupt #30 - SINT31 0xF8 18 Software interrup...
Page 55 - Table 1-34. IFR1 and IER1 Bit Descriptions
www.ti.com Interrupts The interrupt flag register (IFR1) and interrupt enable register 1 (IER1) bit layouts are shown in Figure 1-26 and described in Table 1-34 . Figure 1-26. IFR1 and IER1 Bit Locations 15 11 10 9 8 Reserved RTOS DLOG BERR R-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 I2C EMIF GPIO USB SPI...
Page 56 - SPRUFO2; GPIO Interrupt Enable and Aggregation Flag Registers; SPRUFO4; DMA Interrupt Enable and Aggregation Flag Registers; SPRUFO9
Interrupts www.ti.com 1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h] The CPU has only one interrupt flag that is shared among the three timers. The CPU's interrupt flag is bit4 (TINT) of the IFR0 & IER0 registers (see Figure 1-25). Since the interrupt flag is shared, software mu...
Page 57 - System Configuration and Control; CPU Word
www.ti.com System Configuration and Control 1.7 System Configuration and Control 1.7.1 Overview The DSP includes system-level registers for controlling, configuring, and reading status of the device.These registers are accessible by the CPU and support the following features: • Device Identification...
Page 60 - The die ID register 6 (DIEIDR6) is shown in
System Configuration and Control www.ti.com 1.7.2.7 Die ID Register 6 (DIEIDR6) [1C46h] The die ID register 6 (DIEIDR6) is shown in Figure 1-33 and described in Table 1-42 . Figure 1-33. Die ID Register 6 (DIEIDR6) [1C46h] 15 0 Reserved R LEGEND: R = Read only; -n = value after reset Table 1-42. Die...
Page 61 - The external bus selection register (EBSR) is shown in
www.ti.com System Configuration and Control 1.7.3 Device Configuration The DSP includes registers for configuring pin multiplexing, the pin output slew rate, the internal pull-upsand pull-downs, DSP_LDO voltage selection and USB_LDO enable. 1.7.3.1 External Bus Selection Register (EBSR) The external...
Page 62 - Table 1-44. EBSR Register Bit Descriptions Field Descriptions
System Configuration and Control www.ti.com Table 1-44. EBSR Register Bit Descriptions Field Descriptions Bit Field Value Description 15 Reserved 0 Reserved. Read-only, writes have no effect. 14-12 PPMODE Parallel Port Mode Control Bits. These bits control the pin multiplexing of the LCD Controller,...
Page 63 - LDO Control
www.ti.com System Configuration and Control Table 1-44. EBSR Register Bit Descriptions Field Descriptions (continued) Bit Field Value Description 2 A17_MODE A17 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 17 (EM_A[17]) andgeneral-purpose input/output pin 23 (GP[23]) pin ...
Page 64 - Table 1-45. RTCPMGT Register Bit Descriptions Field Descriptions
System Configuration and Control www.ti.com Table 1-45. RTCPMGT Register Bit Descriptions Field Descriptions Bit Field Value Description 15-5 Reserved 0 Reserved. Read-only, writes have no effect. 4 WU_DOUT Wakeup output, active low/open-drain. 0 WAKEUP pin driven low. 1 WAKEUP pin is in high-impeda...
Page 65 - Table 1-46. LDOCNTL Register Bit Descriptions Field Descriptions
www.ti.com System Configuration and Control Figure 1-37. LDO Control Register (LDOCNTL) [7004h] 15 8 Reserved R-0 7 2 1 0 Reserved DSP_LDO_V USB_LDO_EN R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-46. LDOCNTL Register Bit Descriptions Field Descriptions Bit...
Page 66 - The output slew rate control register (OSRCR) is shown in
System Configuration and Control www.ti.com 1.7.3.4 Output Slew Rate Control Register (OSRCR) [1C16h] To provide the lowest power consumption setting, the DSP has configurable slew rate control on the EMIFand CLKOUT output pins. The output slew rate control register (OSRCR) is used to set a subset o...
Page 70 - SPRUFT2
System Configuration and Control www.ti.com Table 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions (continued) Bit Field Value Description 10 PD10PD Parallel port pin 10 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down. 0 Pin pull-down is enabled. 1...
Page 71 - DMA Synchronization Events; The system-level DMA registers are listed in; Table 1-53. System Registers Related to the DMA Controllers
www.ti.com System Configuration and Control 1.7.4.1 DMA Synchronization Events The DMA controllers allow activity in their channels to be synchronized to selected events. The DSPsupports 20 separate synchronization events and each channel can be tied to separate sync eventsindependent of the other c...
Page 75 - CPU accesses to NAND Flash devices and EMIF registers.
www.ti.com System Configuration and Control Table 1-59. Peripheral Reset Control Register (PRCR) Field Descriptions (continued) Bit Field Value Description 5 PG3_RST Peripheral group 3 software reset bit. Drives the MMC/SD0, MMC/SD1, I2S0, and I2S1 reset signal. Write 0 Writing zero has no effect Wr...
Page 76 - Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses; The USB system control register (USBSCR) is described in; Table 1-61. Effect of USBSCR BYTEMODE Bits on USB Access; The EMIF system control register (ESCR) is shown in
System Configuration and Control www.ti.com Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses BYTEMODE Setting CPU Access to EMIF Register CPU Access To External Memory BYTEMODE = 00b (16-bit Entire register contents are accessed ASIZE = 01b (16-bit data bus): EMIF generates a word access) single...
Page 77 - The EMIF clock divider register (ECDR) is shown in
www.ti.com System Configuration and Control 1.7.7 EMIF Clock Divider Register (ECDR) [1C26h] The EMIF clock divider register (ECDR) controls the input clock frequency to the EMIF module. WhenEDIV = 1 (default), the EMIF operates at the same clock rate as the system clock (SYSCLK). When EDIV= 0, the ...
Page 78 - IMPORTANT NOTICE; Products
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...
