Texas Instruments TMS320VC5402 - Manual

Texas Instruments TMS320VC5402

Texas Instruments TMS320VC5402 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.

1 Page 1
2 Page 2
3 Page 3
4 Page 4
5 Page 5
6 Page 6
7 Page 7
8 Page 8
9 Page 9
10 Page 10
11 Page 11
12 Page 12
13 Page 13
14 Page 14
15 Page 15
16 Page 16
17 Page 17
18 Page 18
19 Page 19
20 Page 20
21 Page 21
22 Page 22
23 Page 23
24 Page 24
25 Page 25
26 Page 26
27 Page 27
28 Page 28
29 Page 29
30 Page 30
31 Page 31
32 Page 32
33 Page 33
34 Page 34
35 Page 35
36 Page 36
37 Page 37
38 Page 38
39 Page 39
40 Page 40
41 Page 41
42 Page 42
43 Page 43
44 Page 44
45 Page 45
46 Page 46
47 Page 47
48 Page 48
49 Page 49
50 Page 50
51 Page 51
52 Page 52
53 Page 53
54 Page 54
55 Page 55
56 Page 56
57 Page 57
58 Page 58
59 Page 59
60 Page 60
61 Page 61
62 Page 62
63 Page 63
64 Page 64
65 Page 65
66 Page 66
67 Page 67
68 Page 68
69 Page 69
Page: / 69

Table of Contents:

  • Page 3 – description
  • Page 12 – memory; on-chip ROM with bootloader; TMS320C54x DSP CPU and Peripherals Reference Set,
  • Page 14 – Twenty address lines, instead of sixteen
  • Page 15 – Figure 3. Extended Program Memory
  • Page 16 – software-programmable wait-state generator
  • Page 18 – programmable bank-switching wait states
  • Page 20 – multichannel buffered serial ports
  • Page 21 – multichannel buffered serial ports (continued); Frame synchronization pulse width; hardware timer
  • Page 22 – Table 5. Clock Mode Settings at Reset
  • Page 23 – The DMA has the following features:; DMA memory map
  • Page 27 – memory-mapped registers
  • Page 28 – Table 10. Peripheral Memory-Mapped Registers
  • Page 29 – McBSP control registers and subaddresses; Table 11. McBSP Control Registers and Subaddresses; DMA subbank addressed registers
  • Page 30 – DMA subbank addressed registers (continued); Table 12. DMA Subbank Addressed Registers
  • Page 31 – interrupts; Table 13. Interrupt Locations and Priorities
  • Page 33 – documentation support
  • Page 34 – Supply voltage core range, CV; DD; Input voltage range, V; stg; recommended operating conditions
  • Page 35 – PARAMETER MEASUREMENT INFORMATION
  • Page 36 – internal oscillator with external crystal; and power dissipation of 1 mW.; Figure 10. Internal Oscillator With External Crystal
  • Page 37 – Figure 11, and the recommended operating conditions table)
  • Page 41 – memory write
  • Page 44 – parallel I/O port write
  • Page 45 – Figure 17. Memory Read With Externally Generated Wait States
  • Page 46 – ready timing for externally generated wait states (continued); Figure 18. Memory Write With Externally Generated Wait States
  • Page 47 – Figure 19. I/O Read With Externally Generated Wait States
  • Page 48 – Figure 20. I/O Write With Externally Generated Wait States
  • Page 51 – Figure 22. Reset and BIO Timings; Figure 23. Interrupt Timing
  • Page 52 – Figure 25. IAQ and IACK Timings
  • Page 53 – Figure 27. TOUT Timing
  • Page 54 – multichannel buffered serial port timing
  • Page 55 – multichannel buffered serial port timing (continued); Figure 28. McBSP Receive Timings
  • Page 61 – HPI8 timing
  • Page 62 – timing requirements
  • Page 65 – MECHANICAL DATA; PLASTIC QUAD FLATPACK
  • Page 66 – PLASTIC BALL GRID ARRAY PACKAGE
  • Page 67 – PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
Loading the manual

/

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000

1

POST OFFICE BOX 1443

•

HOUSTON, TEXAS 77251–1443

Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus

40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators

17-

×

17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation

Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator

Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle

Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)

Data Bus With a Bus-Holder Feature

Extended Addressing Mode for 1M

×

16-Bit

Maximum Addressable External Program
Space

4K x 16-Bit On-Chip ROM

16K x 16-Bit Dual-Access On-Chip RAM

Single-Instruction-Repeat and
Block-Repeat Operations for Program Code

Block-Memory-Move Instructions for
Efficient Program and Data Management

Instructions With a 32-Bit Long Word
Operand

Instructions With Two- or Three-Operand
Reads

Arithmetic Instructions With Parallel Store
and Parallel Load

Conditional Store Instructions

Fast Return From Interrupt

On-Chip Peripherals
– Software-Programmable Wait-State

Generator and Programmable Bank
Switching

– On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or
External Clock Source

– Two Multichannel Buffered Serial Ports

(McBSPs)

– Enhanced 8-Bit Parallel Host-Port

Interface (HPI8)

– Two 16-Bit Timers
– Six-Channel Direct Memory Access

(DMA) Controller

Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1

†

(JTAG) Boundary Scan

Logic

10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (1.8-V Core)

Available in a 144-Pin Plastic Low-Profile
Quad Flatpack (LQFP) (PGE Suffix) and a
144-Pin Ball Grid Array (BGA) (GGU Suffix)

NOTE:This data sheet is designed to be used in conjunction with the

TMS320C5000 DSP Family Functional Overview

(literature number SPRU307).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright

2000, Texas Instruments Incorporated

† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

"%&($*"&% ") +((%* ) & '+#"*"&% *

(&+*) &%&($ *& )'""*"&%) '( *! *($) & -) %)*(+$%*)

)*%( ,((%*. (&+*"&% '(&))"% &) %&* %))("#. "%#+

*)*"% & ## '($*()

查询TMS320VC5402供应商

"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.

Summary

Page 3 - description

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5402 unlessotherwise specified) is based on an advanced modified Harvard architecture that has one ...

Page 12 - memory; on-chip ROM with bootloader; TMS320C54x DSP CPU and Peripherals Reference Set,

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory The ’5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration. on-chip ROM with bootloader The ’5402 features a 4K-word × 16-bit on-chip maskable ROM. C...

Page 14 - Twenty address lines, instead of sixteen

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 relocatable interrupt vector table (continued) 15 7 6 5 4 3 2 1 0 IPTR MP/MC OVLY AVIS DROM CLK OFF SMUL SST R/W R/W R/W R R R R/W R/W LEGEND: R = Read, W = Write Figure 2. Processor Mode Status (PMST) ...

Other Texas Instruments Models

All Texas Instruments Other