Page 6 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; . Tip: Enter the literature number in the; SPRUEP8
Preface SPRUEQ7C – February 2010 Read This First About This Manual This document describes the asynchronous external memory interface (EMIF) in the TMS320DM646xDigital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of externaldevices. Notational Conventions This do...
Page 8 - Introduction; Purpose of the Peripheral
User's Guide SPRUEQ7C – February 2010 Asynchronous External Memory Interface (EMIF) 1 Introduction This document describes the operation of the asynchronous external memory interface (EMIF) in theTMS320DM646x Digital Media System-on-Chip (DMSoC). 1.1 Purpose of the Peripheral The purpose of this EMI...
Page 9 - Functional Block Diagram; Figure 1; Figure 1. EMIF Functional Block Diagram; Architecture; Clock Control; SPRUEP9; EMIF Requests
EM_CS[5:2] EM_OE EM_RW EM_WAIT[5:2] EM_WE EM_BA[1:0] EM_D[15:0] EM_A[22:0] EMIF SCR VICP DSP ARM EDMA3 Master peripherals www.ti.com Architecture 1.3 Functional Block Diagram Figure 1 illustrates the connections between the EMIF and its internal requesters, along with the external EMIF pins. Section...
Page 10 - Signal Descriptions; Table 1; Description; Pin Multiplexing; Normal mode; Table 2. Behavior of EM_CS Signal Between Normal Mode and; Mode
Architecture www.ti.com 2.3 Signal Descriptions Table 1 describes the function of each of the EMIF pins. Table 1. EMIF Pins Pins(s) I/O Description EM_ A[22:0] O EMIF address bus. These pins are used in conjunction with the EM_BA pins to form the address that issent to the device. EM_BA[1:0] O EMIF ...
Page 11 - EMIF; Interfacing to Asynchronous Memory; Figure 2; Figure 2. EMIF Asynchronous Interface
EM_CS[5:2] EM_WE EM_OE EM_RW EM_WAIT[5:2] EM_BA[1:0] EM_D[15:0] EM_A[22:0] EMIF EM_D[7:0] EM_A[21:0] EM_BA[1:0] DQ[7:0] A[23:2] A[1:0] EMIF 8−bit asynchronous memory a) EMIF to 8-bit memory interface EM_D[15:0] EM_A[21:0] EM_BA[1] DQ[15:0] A[22:1] A[0] EMIF 16−bit asynchronous memory b) EMIF to 16-b...
Page 12 - Programmable Asynchronous Parameters; Section 4; Parameter; Extended Wait mode enable.
Architecture www.ti.com 2.5.2 Programmable Asynchronous Parameters The EMIF allows a high degree of programmability for shaping asynchronous accesses. Theprogrammable parameters are:• Setup: The time between the beginning of a memory cycle (address valid) and the activation of theoutput enable or wr...
Page 13 - Table 5. Description of the EMIF Interrupt Mask Set Register (EIMSR)
www.ti.com Architecture Table 3. Description of the Asynchronous Configuration Register (ACFGn) (continued) Parameter Description ASIZE Asynchronous Device Bus Width.This field determines the data bus width of the asynchronous interface in the following way: • ASIZE = 0 selects an 8-bit bus • ASIZE ...
Page 14 - Read and Write Operations in Normal Mode; Asynchronous Read Operations (Normal Mode); Table 7. Asynchronous Read Operation in Normal Mode; Time Interval
Architecture www.ti.com 2.5.4 Read and Write Operations in Normal Mode Normal mode is the asynchronous interface's default mode of operation. The Normal mode is selectedwhen the SS bit in the asynchronous configuration register (ACFGn) is cleared to 0. In this mode, theEM_CS signal operates as a chi...
Page 16 - Asynchronous Write Operations (Normal Mode); Table 8. Asynchronous Write Operation in Normal Mode
Architecture www.ti.com 2.5.4.2 Asynchronous Write Operations (Normal Mode) An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write to asynchronous memory. In the event that the write request cannot be serviced by a single access cycleto the external de...
Page 18 - Read and Write Operations in Select Strobe Mode; Asynchronous Read Operations (Select Strobe Mode); Table 9. Asynchronous Read Operation in Select Strobe Mode
Architecture www.ti.com 2.5.5 Read and Write Operations in Select Strobe Mode Select Strobe mode is the EMIF's second mode of operation. The SS mode is selected when the SS bit inthe asynchronous configuration register (ACFGn) is set to 1. In this mode, the EM_CS pin functions as astrobe signal and ...
Page 20 - Asynchronous Write Operations (Select Strobe Mode); Table 10. Asynchronous Write Operation in Select Strobe Mode
Architecture www.ti.com 2.5.5.2 Asynchronous Write Operations (Select Strobe Mode) An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write to memory in the asynchronous bank of the EMIF. In the event that the write request cannot be servicedby a single ...
Page 22 - NAND Flash Mode; Configuring for NAND Flash Mode; Table 12. Configuration For NAND Flash
Architecture www.ti.com 2.5.6 NAND Flash Mode NAND Flash mode is the EMIF's third mode of operation. Each chip select space may be placed in NANDFlash mode individually by setting the appropriate CSnNAND bit in the NAND Flash control register(NANDFCR). Table 11 displays the bit fields present in NAN...
Page 23 - Connecting to NAND Flash; must be controlled outside of the EMIF.; Figure 8. EMIF to NAND Flash Interface; Driving CLE and ALE
CLE_EM_A[16] ALE_EM_A[17] EM_CS[n] EM_WE EM_OE EM_D[7:0] EM_WAIT[n] EMIF CLE ALE CE WE OE IO[7:0] R/B NAND flash a) Connection to 8-bit NAND device b) Connection to 16-bit NAND device EM_WAIT[n] EM_D[15:0] EM_OE EM_WE EM_CS[n] ALE_EM_A[17] CLE_EM_A[16] EMIF CE IO[15:0] R/B OE WE NAND flash CLE ALE w...
Page 24 - NAND Read and Program Operations; remain low during the t; NAND Data Read and Write via DMA
Architecture www.ti.com 2.5.6.4 NAND Read and Program Operations A NAND Flash access cycle is composed of a command, address, and data phase. The EMIF will notautomatically generate these three phases to complete a NAND access with one transfer request. Tocomplete a NAND access cycle, multiple singl...
Page 25 - ECC Generation
Bit 7Bit 7 Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 6 Bit 5 Bit 4 Bit 2 Bit 3 Bit 1 Bit 0 Bit 6 Bit 6 Bit 1 Bit 3 Bit 2 Bit 4 Bit 5 Bit 5 Bit 4 Bit 2 Bit 3 Bit 1 Bit 0 Bit 0 p8o p8o p8e p8e p16e p16o p32e Byte 1Byte 2Byte 3Byte 4 Bit 6 Bit 6 Bit 6 Bit 6 Byte 2 Bit 7 Byte 4 Byte 3 Bi...
Page 26 - Interfacing to a Non-CE Don't Care NAND Flash; Interfacing to a TI DSP HPI
EM_D[15:0] EM_RW EM_A[1:0] EM_WAIT EM_OE EM_WE EM_CS EM_BA1 GPIOx AEMIF HD[15:0] HR/W HCNTL[1:0] HRDY HDS1 HCS HHWIL HINT HDS2 HAS HPIENA HBED A HBE1 A HPI16 VCC VCC VSS VSS Architecture www.ti.com 2.5.6.7 NAND Flash Status Register (NANDFSR) The NAND Flash status register (NANDFSR) indicates the ra...
Page 27 - Extended Wait Mode and the EM_WAIT Pin; for details on enabling this interrupt.; Data Bus Parking
www.ti.com Architecture 2.5.8 Extended Wait Mode and the EM_WAIT Pin The Extended Wait mode is a mode in which the external asynchronous device may assert control overthe length of the strobe period. The Extended Wait mode can be entered by setting the EW bit in theasynchronous configuration registe...
Page 28 - Interrupt Support; Table 13. EMIF Interrupt; Interrupt Events; Table 14. Interrupt Monitor and Control Bit Fields
Architecture www.ti.com 2.5.11 Interrupt Support The EMIF has a single interrupt source ( Table 13 ) mapped to the ARM interrupt controller. For more information on the ARM interrupt controller (AINTC), see the TMS320DM646x DMSoC ARM SubsystemReference Guide ( SPRUEP9 ). Table 13. EMIF Interrupt ARM...
Page 29 - Interrupt Multiplexing; Program Execution; Emulation Considerations
www.ti.com Architecture 2.5.11.2 Interrupt Multiplexing The EMIF interrupt is supported by both the ARM and DSP. The interrupt is not multiplexed with anotherinterrupt and is therefore always available. 2.5.12 Program Execution Since the EMIF does not have byte enable or data mask pins, byte accesse...
Page 30 - Use Cases; and; Connecting to ASRAM
EM_CS EM_WE EM_OE A[18:0] EM_BA[1] EM_D[15:0] CE WE OE LB UB A[19:1] A[0] DQ[15:0] V S S V S S EMIF TC5516100FT−12 Use Cases www.ti.com 3 Use Cases The EMIF allows a high degree of programmability for shaping asynchronous accesses. As previouslystated, the shape and duration of the asynchronous acce...
Page 31 - Meeting AC Timing Requirements for ASRAM; Table 16. ASRAM Output Timing Characteristics; Table 17. ASRAM Input Timing Requirement for a Read
R_SETUP ) R_STROBE w ǒ t ACC (m) ) t SU Ǔ t cyc * 1 R_SETUP ) R_STROBE ) R_HOLD w t RC (m) t cyc * 3 R_HOLD w ǒ t H * t OH (m) Ǔ t cyc * 1 TA w t COD (m) t cyc * 1 www.ti.com Use Cases 3.1.2 Meeting AC Timing Requirements for ASRAM When configuring the EMIF to interface to ASRAM, you must consider t...
Page 32 - Strobe; Figure 12. Timing Waveform of an ASRAM Read; lists the AC timing specifications that must be satisfied.; Table 18. ASRAM Input Timing Requirements for a Write
t RC (m) Strobe Setup Hold EM_CS EM_A[21:0] EM_BA[1:0] EM_OE EM_D[15:0] t ACC (m) t SU t H t COD (m) t OH (m) Use Cases www.ti.com Figure 12. Timing Waveform of an ASRAM Read For a write access, Table 18 lists the AC timing specifications that must be satisfied. Table 18. ASRAM Input Timing Requirem...
Page 33 - From; is the period at which the EMIF operates. The; in the; Figure 13. Timing Waveform of an ASRAM Write
W_STROBE w t WP (m) t cyc * 1 W_SETUP ) W_STROBE w max ǒ t AW (m) t cyc , t DS (m) t cyc Ǔ * 1 W_HOLD w max ǒ t WR (m) t cyc , t DH (m) t cyc Ǔ * 1 W_SETUP ) W_STROBE ) W_HOLD w t WC (m) t cyc * 3 t WC (m) Strobe Setup Hold t WR (m) t WP (m) t AW (m) t DS (m) t DH (m) EM_CS EM_A[21:0] EM_BA[1:0] EM_...
Page 34 - Taking Into Account PCB Delays
R_SETUP ) R_STROBE w ǒ t EM_A ) t ACC (m) ) t SU ) t EM_D Ǔ t cyc * 1 R_SETUP ) R_STROBE ) R_HOLD w t RC (m) t cyc * 3 R_HOLD w ǒ t H * t EM_D * t OH (m) * t EM_A Ǔ t cyc * 1 TA w ǒ t EM_CS ) t COD (m) ) t EM_D Ǔ t cyc * 1 Use Cases www.ti.com 3.1.3 Taking Into Account PCB Delays The equations descr...
Page 35 - Figure 14. Timing Waveform of an ASRAM Read with PCB Delays
1 Setup 2 Strobe 3 Hold 4 EM_CS EM_CS (ASRAM) EM_A[21:0]/ EM_BA[1:0] EM_A[21:0]/ EM_BA[1:0] (ASRAM) EM_OE EM_OE (ASRAM) EM_D[15:0] EM_D[15:0] (ASRAM) t CS t CS t RC (m) t EM_A t EM_A t EM_OE t EM_OE t SU t EM_D t ACC (m) t EM_D t OH (m) t H t COD (m) www.ti.com Use Cases Figure 14. Timing Waveform o...
Page 36 - Setup; Figure 15. Timing Waveform of an ASRAM Write with PCB Delays
W_STROBE w t WP (m) t cyc * 1 W_SETUP ) W_STROBE w max ǒ ǒ t EM_A ) t AW (m) * t EM_WE Ǔ t cyc , ǒ t EM_D ) t DS (m) * t EM_WE Ǔ t cyc Ǔ * 1 W_HOLD w max ǒ ǒ t EM_WE ) t WR (m) * t EM_A Ǔ t cyc , ǒ t EM_WE ) t DH (m) * t EM_D Ǔ t cyc Ǔ * 1 W_SETUP ) W_STROBE ) W_HOLD w t WC (m) t cyc * 3 1 Setup 2 S...
Page 37 - EMIF clock speed is 100 MHZ (t; lists the data sheet specifications for the EMIF and
www.ti.com Use Cases 3.1.4 Example Using TC5516100FT-12 This section takes you through the configuration steps required to implement Toshiba’s TC55V1664FT-12ASRAM with the EMIF. The following assumptions are made: • ASRAM is connected to chip select space 3 (EM_CS[3]) • EMIF clock speed is 100 MHZ (...
Page 39 - Interfacing to NAND Flash; describes how to connect the EMIF to the HY27UA081G1M.; Margin Requirements
www.ti.com Use Cases Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fieldsare equal to EMIF clock cycles minus 1 cycle, the A2CR should be configured as in Table 23 . In this example, the EM_WAIT signal is not implemented; therefore, the asynchronous wait cycle conf...
Page 40 - Meeting AC Timing Requirements for NAND Flash; As described in; Table 25. EMIF Read Timing Requirements; Table 26. NAND Flash Read Timing Requirements
Use Cases www.ti.com 3.2.2 Meeting AC Timing Requirements for NAND Flash When configuring the EMIF to interface to NAND Flash, you must consider the AC timing requirements ofthe NAND Flash as well as the AC timing requirements of the EMIF. These can be found in the data sheetfor each respective devi...
Page 41 - Figure 16. Timing Waveform of a NAND Flash Read
R_SETUP w t CLR (m) t cyc * 1 R_STROBE w max ǒ ǒ t REA (m) ) t SU Ǔ t cyc , t RP (m) t cyc Ǔ * 1 R_SETUP ) R_STROBE w ǒ t CEA (m) ) t SU Ǔ t cyc * 1 R_HOLD w ǒ t H * t CHZ (m) Ǔ t cyc * 1 R_SETUP ) R_STROBE ) R_HOLD w t RC (m) t cyc * 3 TA w max ǒ t CHZ (m) t cyc , t RHZ (m) * (R_HOLD ) 1)t cyc t cy...
Page 42 - Table 27. NAND Flash Write Timing Requirements
W_SETUP w max ǒ t CLS (m) t cyc , t ALS (m) t cyc , t CS (m) t cyc Ǔ * 1 W_STROBE w t WP (m) t cyc * 1 W_SETUP ) W_STROBE w t DS (m) t cyc * 1 W_HOLD w max ǒ t CLH (m) t cyc , t ALH (m) t cyc , t CH (m) t cyc , t DH (m) t cyc Ǔ * 1 W_SETUP ) W_STROBE ) W_HOLD w t WC (m) t cyc * 3 Use Cases www.ti.co...
Page 43 - Figure 17. Timing Waveform of a NAND Flash Command Write
t CH (m) t WC (m) t ALH (m) t CLH (m) t WP (m) EM_CS ALE_EM_A[1] CLE_EM_A[2] EM_WE EM_D[7:0] t CS (m) t ALS (m) t CLS (m) t DS (m) t DH (m) Setup Strobe Hold t CH (m) t WC (m) t ALH (m) t CLH (m) t WP (m) EM_CS ALE_EM_A[1] CLE_EM_A[2] EM_WE EM_D[7:0] t CS (m) t ALS (m) t CLS (m) t DS (m) t DH (m) Se...
Page 44 - Figure 19. Timing Waveform of a NAND Flash Data Write
t CH (m) t WC (m) t ALH (m) t CLH (m) t WP (m) EM_CS ALE_EM_A[1] CLE_EM_A[2] EM_WE EM_D[7:0] t CS (m) t ALS (m) t CLS (m) t DS (m) t DH (m) Setup Strobe Hold Use Cases www.ti.com Figure 19. Timing Waveform of a NAND Flash Data Write 44 Asynchronous External Memory Interface (EMIF) SPRUEQ7C – Februar...
Page 45 - Table 28. EMIF Timing Requirements for HY27UA081G1M Example
www.ti.com Use Cases 3.2.3 Example Using Hynix HY27UA081G1M This section takes you through the configuration steps required to implement Hynix’s HY27UA081G1MNAND Flash with the EMIF. The following assumptions are made: • NAND Flash is connected to chip select space 2 (EM_CS[2]) • EMIF clock speed is...
Page 46 - Therefore with a 10 nS margin added in, R_SETUP
R_SETUP w t CLR (m) t cyc * 1 w ǒ 1010 Ǔ * 1 w 0 R_STROBE w max ǒ ǒ t REA (m) ) t SU Ǔ t cyc , t RP t cyc Ǔ * 1 w ǒ 6510 Ǔ * 1 w 5.5 R_SETUP ) R_STROBE w ǒ t CEA ) t SU Ǔ t cyc * 1 w (75 ) 5) 10 * 1 w 7 R_HOLD w ǒ t H * t CHZ (m) Ǔ t cyc * 1 w (0 * 20) 10 * 1 w * 3 R_SETUP ) R_STROBE ) R_HOLD w t RC...
Page 47 - Table 31. Configuring NANDFCR for HY27UA081G1M Example
www.ti.com Use Cases Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fieldsare equal to EMIF clock cycles minus 1 cycle, the A1CR should be configured as in Table 30 . In this example, although the EM_WAIT signal is connected to the R/B signal of the NAND Flash the E...
Page 48 - Registers; should; Offset
Registers www.ti.com 4 Registers The external memory interface (EMIF) is controlled by programming its internal memory-mapped registers(MMRs). Table 32 lists the memory-mapped registers for the EMIF. See the device-specific data manual for the memory address of these registers. All other register of...
Page 49 - The revision code and status register (RCSR) is shown in; Bit
www.ti.com Registers 4.1 Revision Code and Status Register (RCSR) The revision code and status register (RCSR) is shown in Figure 20 and described in Table 33 . Figure 20. Revision Code and Status Register (RCSR) 31 30 29 16 Reserved MODID R-x R-Fh 15 8 7 0 REVMAJ REVMIN R-2h R-2h LEGEND: R = Read o...
Page 50 - Asynchronous Wait Cycle Configuration Register (AWCCR); and described in; insertion of extended wait cycles.; Figure 21. Asynchronous Wait Cycle Configuration Register (AWCCR)
Registers www.ti.com 4.2 Asynchronous Wait Cycle Configuration Register (AWCCR) The asynchronous wait cycle configuration register (AWCCR) is used to configure the parameters forextended wait cycles. Both the polarity of the EM_WAIT[5:2] pins and the maximum allowable number ofextended wait cycles c...
Page 53 - Table 36. EMIF Interrupt Raw Register (EIRR) Field Descriptions
www.ti.com Registers 4.4 EMIF Interrupt Raw Register (EIRR) The EMIF interrupt raw register (EIRR) is used to monitor and clear the EMIF’s hardware-generatedinterrupts. The bits in EIRR are set when an interrupt condition occurs, regardless of the status of theEMIF interrupt mask set register (EIMSR...
Page 54 - Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions
Registers www.ti.com 4.5 EMIF Interrupt Mask Register (EIMR) Similar to the EMIF interrupt raw register (EIRR), the EMIF interrupt mask register (EIMR) is used tomonitor and clear the status of the EMIF’s hardware-generated interrupts. The main difference betweenthe two registers is that when the bi...
Page 58 - EMIF Interrupt Mask Clear Register (EIMCR)
Registers www.ti.com 4.7 EMIF Interrupt Mask Clear Register (EIMCR) The EMIF interrupt mask clear register (EIMCR) is used to disable the interrupts. If a bit is read as 1, thecorresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when theassociated interru...
Page 60 - The NAND Flash control register (NANDFCR) is shown in; Table 40. NAND Flash Control Register (NANDFCR) Field Descriptions
Registers www.ti.com 4.8 NAND Flash Control Register (NANDFCR) The NAND Flash control register (NANDFCR) is shown in Figure 27 and described in Table 40 . Figure 27. NAND Flash Control Register (NANDFCR) 31 16 Reserved R-0 15 12 11 10 9 8 Reserved CS5ECC CS4ECC CS3ECC CS2ECC R-0 R/W-0 R/W-0 R/W-0 R/...
Page 61 - The NAND Flash status register (NANDFSR) is shown in; Table 41. NAND Flash Status Register (NANDFSR) Field Descriptions; The NAND Flash n ECC register (NANDECCn) is shown in
www.ti.com Registers 4.9 NAND Flash Status Register (NANDFSR) The NAND Flash status register (NANDFSR) is shown in Figure 28 and described in Table 41 . Figure 28. NAND Flash Status Register (NANDFSR) 31 16 Reserved R-0 15 4 3 0 Reserved WAITST R-0 R-0 LEGEND: R = Read only; -n = value after reset T...
Page 62 - Table 42. NAND Flash n ECC Register (NANDECCn) Field Descriptions
Registers www.ti.com Figure 29. NAND Flash n ECC Register (NANDECCn) 31 28 27 26 25 24 Reserved P2048O P1024O P512O P256O R-0 R-0 R-0 R-0 R-0 23 22 21 20 19 18 17 16 P128O P64O P32O P16O P8O P4O P2O P1O R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 15 12 11 10 9 8 Reserved P2048E P1024E P512E P256E R-0 R-0 R-0 R-...
Page 63 - Appendix A Revision History; Table 43. Document Revision History; Reference
www.ti.com Appendix A Revision History Table 43 lists the changes made since the previous version of this document. Table 43. Document Revision History Reference Additions/Modifications/Deletions Figure 1 Changed figure. Table 1 Changed table. Figure 2 Changed figure. Section 2.5.6.2 Changed paragra...
Page 64 - IMPORTANT NOTICE; Products
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...
