Texas Instruments TMS320DM355 - Manual

Texas Instruments TMS320DM355

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Table of Contents:

  • Page 2 – PRODUCT PREVIEW; 0nm Process Technology
  • Page 4 – Functional Block Diagram; shows the functional block diagram of the DM355 device.
  • Page 5 – Contents
  • Page 6 – Device Characteristics; Table 2-1. Characteristics of the Processor; HARDWARE FEATURES
  • Page 7 – Memory Map Summary; shows the memory map address ranges of the device.; Table 2-3. DM355 ARM Configuration Bus Access to Peripherals
  • Page 8 – Address
  • Page 9 – through
  • Page 13 – Image Data Input - Video Processing Front End; The pin functions tables (; Table 2-4. CCD Controller Signals for Each Input Mode; PIN NAME
  • Page 14 – TERMINAL
  • Page 15 – and
  • Page 16 – Table 2-6. Signals for VPBE Display Modes
  • Page 17 – Table 2-7. Digital Video Terminal Functions
  • Page 18 – Asynchronous External Memory Interface (AEMIF); Table 2-8. Analog Video Terminal Functions
  • Page 20 – DDR Memory Interface; The DDR EMIF supports DDR2 and mobile DDR.
  • Page 22 – GPIO
  • Page 29 – Audio Interfaces
  • Page 30 – UART Interface
  • Page 31 – C Interface; The includes an I; C Terminal Functions
  • Page 32 – The provides interface with the system clocks.
  • Page 34 – The provides interfaces for system configuration and boot load.
  • Page 35 – The emulation interface allow software and hardware debugging.
  • Page 36 – provides a complete pin description list in pin number order.
  • Page 55 – Development Tools; . For information on pricing and
  • Page 56 – Device Documentation; This document; SPRUFB3
  • Page 57 – DMSoC
  • Page 58 – SPRUEE7
  • Page 59 – Detailed Device Description; ARM Subsystem Overview; Components of the ARM Subsystem
  • Page 60 – Figure 3-1. DM355 ARM Subsystem Block Diagram
  • Page 61 – MMU; Hardware page table walks
  • Page 62 – Memory Mapping; ARM Internal Memories
  • Page 63 – External Memories
  • Page 65 – Overview; . The PLLs are described further in
  • Page 66 – Sequencer; Figure 3-2. Device Clocking Block Diagram
  • Page 67 – Supported Clocking Configurations for DM355-216
  • Page 69 – Supported Clocking Configurations for DM355-270
  • Page 71 – Peripheral Clocking Considerations; 4 MHz crystal input at MXI1; NOTE; For proper USB function, SYSCLK2 must be greater than 60 MHz.
  • Page 73 – PLL Controller Module
  • Page 74 – Output Clock
  • Page 76 – PLLC2 Configuration in DM355
  • Page 77 – System Control Module
  • Page 78 – Hardware Controlled Pin Multiplexing; Deep sleep and fast NAND boot control; Peripheral
  • Page 79 – Software Controlled Pin Multiplexing; and further described in the ARM; Type
  • Page 80 – Default Device Configurations; for more information on the boot process.; The device configuration pins are described in
  • Page 81 – Power Domain and Module State Configuration
  • Page 83 – Device Boot Modes; Default States; Boot modes are further described in
  • Page 84 – for information on the boot selection pins.
  • Page 85 – Power Management; The general boot sequence is shown in; Figure 3-6. Boot Mode Functional Block Diagram
  • Page 86 – Power Management Features
  • Page 87 – Slave Module
  • Page 89 – EDMA Channel Synchronization Events; EDMA
  • Page 91 – Device Operating Conditions
  • Page 92 – Recommended Operating Conditions; MIN NOM
  • Page 93 – Case Temperature (Unless Otherwise Noted)
  • Page 94 – Parameter Information Device-Specific Information; Tester Pin Electronics; Signal Transition Levels; Figure 5-1. Test Load Circuit for AC Timing Measurements; All input and output timing parameters are referenced to V; Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels
  • Page 95 – Timing Parameters and Board Routing Analysis
  • Page 96 – Recommended Clock and Control Signal Transition Behavior; All clocks and control signals should transition between V; and V; and V; The power supplies of DM355 are summarized in
  • Page 97 – Power-Supply Sequencing; for a description of DM355 power supplies.; Power-Supply Design Considerations; placed outside of the BGA footprint.
  • Page 98 – Reset Electrical Data/Timing; UNIT
  • Page 99 – Oscillators and Clocks; circuit shown in
  • Page 100 – . The external crystal load capacitors must be connected only to; shown in; Oscillator
  • Page 103 – PARAMETER
  • Page 104 – GPIO Peripheral Input/Output Electrical Data/Timing; The GPIO peripheral supports the following:
  • Page 105 – GPIO Peripheral External Interrupts Electrical Data/Timing; Figure 5-13. GPIO External Interrupt Timing
  • Page 107 – AEMIF Electrical Data/Timing
  • Page 108 – Memory Cycles for AEMIF Module (see
  • Page 109 – UNI; Figure 5-14. Asynchronous Memory Read Timing for EMIF
  • Page 111 – Figure 5-18. Synchronous OneNAND Flash Read Timing
  • Page 112 – DDR2 Memory Controller
  • Page 115 – SPRUEC8
  • Page 116 – Support for program lens shading correction.
  • Page 120 – Support for 2 ROM tables, one of which can be selected at a given time
  • Page 123 – Figure 5-28. VPBE Input Timing With Respect to PCLK and EXTCLK
  • Page 124 – Data Output With Respect to VCLK
  • Page 125 – Figure 5-31. DAC Only Application Example
  • Page 128 – Figure 5-34. USB Reference Resistor Routing
  • Page 134 – to/from the DM355 through the I2C module.
  • Page 135 – I2C Electrical Data/Timing; Table 5-33. Timing Requirements for I2C Timings
  • Page 136 – Table 5-34. Switching Characteristics for I2C Timings; CAUTION
  • Page 138 – ASP Electrical Data/Timing
  • Page 140 – Table 5-37. ASP as SPI Timing Requirements
  • Page 141 – Table 5-39. ASP as SPI Timing Requirements
  • Page 142 – Table 5-41. ASP as SPI Timing Requirements
  • Page 143 – Table 5-43. ASP as SPI Timing Requirements
  • Page 144 – Timer Electrical Data/Timing; Table 5-45. Timing Requirements for Timer Input
  • Page 145 – 2-bit period counter; Outputs
  • Page 147 – The Real Time Out (RTO) peripheral supports the following features:
  • Page 148 – The JTAG
  • Page 151 – Revision History; Updated DM355 Pin Descriptions table, etc.
  • Page 153 – Mechanical Data; Thermal Data for ZCE
  • Page 155 – IMPORTANT NOTICE; Products
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PRODUCT PREVIEW

1

TMS320DM355 Digital Media System-on-Chip (DMSoC)

1.1 Features

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

encoder

•

High-Performance Digital Media
System-on-Chip

•

External Memory Interfaces (EMIFs)

–

216- and 270-MHz ARM926EJ-S Clock Rate

–

DDR2 and mDDR SDRAM 16-bit wide EMIF
With 256 MByte Address Space (1.8-V I/O)

–

Fully Software-Compatible With ARM9

–

Asynchronous16-/8-bit Wide EMIF (AEMIF)

•

ARM926EJ-S Core

•

Flash Memory Interfaces

–

Support for 32-Bit and 16-Bit (Thumb Mode)

–

NAND (8-/16-bit Wide Data)

Instruction Sets

–

OneNAND(16-bit Wide Data)

–

DSP Instruction Extensions and Single
Cycle MAC

•

Flash Card Interfaces

–

ARM Jazelle Technology

–

Two Multimedia Card (MMC) / Secure

–

EmbeddedICE-RT Logic for Real-Time

Digital (SD/SDIO)

Debug

–

SmartMedia

•

ARM9 Memory Architecture

•

Enhanced Direct-Memory-Access (EDMA)

–

16K-Byte Instruction Cache

Controller (64 Independent Channels)

–

8K-Byte Data Cache

•

USB Port with Integrated 2.0 High-Speed PHY
that Supports

–

32K-Byte RAM

–

USB 2.0 Full and High-Speed Device

–

8K-Byte ROM

–

USB 2.0 Low, Full, and High-Speed Host

–

Little Endian

•

Three 64-Bit General-Purpose Timers (each

•

Video Processing Subsystem

configurable as two 32-bit timers)

–

Front End Provides:

•

One 64-Bit Watch Dog Timer

•

Hardware IPIPE for Real-Time Image
Processing

•

Three UARTs (One fast UART with RTS and
CTS Flow Control)

•

CCD and CMOS Imager Interface

•

Three Serial Port Interfaces (SPI) each with

•

14-Bit Parallel AFE (Analog Front End)

two Chip-Selects

Interface Up to 67.5 MHz

•

One Master/Slave Inter-Integrated Circuit

•

Glueless Interface to Common Video

(I

2

C) Bus™

Decoders

•

BT.601/BT.656 Digital YCbCr 4:2:2

•

Two Audio Serial Port (ASP)

(8-/16-Bit) Interface

–

I2S and TDM I2S

•

Histogram Module

–

AC97 Audio Codec Interface

•

Resize Engine

–

S/PDIF via Software

–

Resize Images From 1/16x to 8x

–

Standard Voice Codec Interface (AIC12)

–

Separate Horizontal/Vertical Control

–

SPI Protocol (Master Mode Only)

–

Two Simultaneous Output Paths

•

Four Pulse Width Modulator (PWM) Outputs

–

Back End Provides:

•

Four RTO (Real Time Out) Outputs

•

Hardware On-Screen Display (OSD)

•

Up to 104 General-Purpose I/O (GPIO) Pins

•

Composite NTSC/PAL video encoder

(Multiplexed with Other Device Functions)

output

•

On-Chip ARM ROM Bootloader (RBL) to Boot

•

8-/16-bit YCC and Up to 18-Bit RGB666

From NAND Flash, MMC/SD, or UART

Digital Output

•

Configurable Power-Saving Modes

•

BT.601/BT.656 Digital YCbCr 4:2:2

•

Crystal or External Clock Input (typically

(8-/16-Bit) Interface

24 MHz or 36 MHz)

•

Supports digital HDTV (720p/1080i)

•

Flexible PLL Clock Generators

output for connection to external

•

Debug Interface Support

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.

I

2

C-bus is a trademark of Texas Instruments.

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All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the

Copyright © 2007–2007, Texas Instruments Incorporated

formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.

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Summary

Page 2 - PRODUCT PREVIEW; 0nm Process Technology

www.ti.com PRODUCT PREVIEW TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 – IEEE-1149.1 (JTAG) • 337-Pin Ball Grid Array (BGA) Package Boundary-Scan-Compatible (ZCE Suffix), 0.65-mm Ball Pitch – ETB (Embedded Trace Buffer) with • 90nm Process Techn...

Page 4 - Functional Block Diagram; shows the functional block diagram of the DM355 device.

www.ti.com PRODUCT PREVIEW 1.3 Functional Block Diagram Peripherals 64bit DMA/Data Bus JTAG 24 MHz 27 MHz (optional) CCD/ CMOS Module DDR2/MDDR 16 CLOCK PLL CLOCK ctrl PLLs JTA JTAG I/F Clocks ARM z ) ARM926EJ-S_Z8 I- cach e 16 K B l-cache 16KB B RA M 32 K B RAM 32KB B D- cach e 8 K D-cache 8KB RO M...

Page 5 - Contents

www.ti.com PRODUCT PREVIEW Contents TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 1 TMS320DM355 Digital Media System-on-Chip 4.2 Recommended Operating Conditions ............... 92 (DMSoC) ................................................... 1 4.3...

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