Page 2 - Pin Configurations; Pin Descriptions
STK17T88 Document Number: 001-52040 Rev. *A Page 2 of 22 Pin Configurations Figure 1. 48-Pin SSOP V SS A 14 A 12 A 7 A 6 DQ 0 DQ 1 V CC DQ 2 A 3 A 2 A 1 V CAP A 13 A 6 A 9 A 11 A 10 DQ 7 DQ 6 V SS A 0 NC 4443424140393837363534333231302928272625 1 2345678910111213141516171819202122 NC E X 1 X 2 2324 ...
Page 3 - Absolute Maximum Ratings; DC Characteristics; STORE
STK17T88 Document Number: 001-52040 Rev. *A Page 3 of 22 Absolute Maximum Ratings Voltage on Input Relative to Ground................. –0.5V to 4.1V Voltage on Input Relative to V SS ...........–0.5V to (V CC + 0.5V) Voltage on DQ 0-7 or HSB ......................–0.5V to (V CC + 0.5V) Temperature u...
Page 4 - AC Test Conditions; Figure 2; Capacitance
STK17T88 Document Number: 001-52040 Rev. *A Page 4 of 22 AC Test Conditions Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times ...................................................≤ 5ns Input and Output Timing Reference Levels ......................
Page 5 - RTC DC Characteristics; RF
STK17T88 Document Number: 001-52040 Rev. *A Page 5 of 22 RTC DC Characteristics Figure 4. RTC Component Configuration Symbol Parameter Commercial Industrial Units Notes Min Max Min Max IBAK RTC Backup Current — 300 — 350 nA From either VRTCcap or VRTCbat VRTCbat RTC Battery Pin Voltage 1.8 3.3 1.8 3...
Page 8 - AutoStore/Power Up RECALL; RECALL
STK17T88 Document Number: 001-52040 Rev. *A Page 8 of 22 AutoStore/Power Up RECALL Figure 9. AutoStore Power Up RECALL Notes 9. t HRECALL starts from the time V CC rises above V SWITCH 10. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place11. Industrial G...
Page 10 - Hardware STORE to SRAM Disabled; Hardware STORE Pulse Width; Soft Sequence Processing Time
STK17T88 Document Number: 001-52040 Rev. *A Page 10 of 22 Hardware STORE Cycle Figure 11. Hardware STORE Cycle Soft Sequence Commands Figure 12. Soft Sequence Command NO. Symbols Parameter STK17T88 Units Notes Standard Alternate Min Max 31 t DELAY t HLQZ Hardware STORE to SRAM Disabled 1 70 µ s 14 3...
Page 11 - MODE Selection; Mode
STK17T88 Document Number: 001-52040 Rev. *A Page 11 of 22 MODE Selection E W G A 14 -A 0 Mode I/O Power Notes H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F Read SRAMRead SRAMRead SRAMRead ...
Page 12 - nvSRAM Operation; SRAM READ; Figure 13. AutoStore Mode; SRAM WRITE; istics
STK17T88 Document Number: 001-52040 Rev. *A Page 12 of 22 nvSRAM Operation The STK17T88 nvSRAM is made up of two functional compo-nents paired in the same physical cell. These are the SRAMmemory cell and a nonvolatile QuantumTrap™ cell. The SRAMmemory cell operates like a standard fast static RAM. D...
Page 13 - Stopping and Starting the RTC Oscillator
STK17T88 Document Number: 001-52040 Rev. *A Page 13 of 22 Software STORE Data can be transferred from the SRAM to the nonvolatilememory by a software address sequence. The STK17T88software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations i...
Page 14 - Real Time Clock; Reading the Clock; Setting; Calibrating The Clock; Capacitor Value
STK17T88 Document Number: 001-52040 Rev. *A Page 14 of 22 Real Time Clock The clock registers maintain time up to 9,999 years inone-second increments. The user can set the time to anycalendar time and the clock automatically keeps track of days ofthe week and month, leap years, and century transitio...
Page 15 - Alarm; Watchdog Timer; Interrupts
STK17T88 Document Number: 001-52040 Rev. *A Page 15 of 22 minute, have one second either shortened by 128 or lengthenedby 256 oscillator cycles. If a binary “1” is loaded into the register, only the first 2 minutesof the 64 minute cycle is modified; if a binary 6 is loaded, the first12 are affected,...
Page 16 - is a functional diagram of the interrupt logic.; Figure 15. Interrupt Block Diagram; Interrupt Register; . When set to a 0, the INT pin is active low; Flags Register
STK17T88 Document Number: 001-52040 Rev. *A Page 16 of 22 Figure 15 is a functional diagram of the interrupt logic. Figure 15. Interrupt Block Diagram Interrupt Register Watchdog Interrupt Enable (WIE). When set to 1, the watchdogtimer drives the INT pin when a watchdog time-out occurs. WhenWIE is s...
Page 17 - RTC Register Map; Register
STK17T88 Document Number: 001-52040 Rev. *A Page 17 of 22 RTC Register Map *A binary value, not a BCD value. 0 - Not implemented, reserved for future use. Default Settings of nonvolatile Calibration and Interrupt registers from factory Calibration Register=00h Interrupt Register=00h The User should ...
Page 18 - Register Map Detail
STK17T88 Document Number: 001-52040 Rev. *A Page 18 of 22 Register Map Detail 0x7FFF Real Time Clock – Years D7 D6 D5 D4 D3 D2 D1 D0 10s Years Years Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibblecontains the value for 10s of years. Each nibble ...
Page 20 - Ordering Codes
STK17T88 Document Number: 001-52040 Rev. *A Page 20 of 22 Ordering Codes 0x7FF0 Flags D7 D6 D5 D4 D3 D2 D1 D0 WDF AF PF OSCF 0 CAL W R WDF Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 withoutbeing reset by the user. It is cleared to 0 when the Fla...
Page 21 - Package Diagram
STK17T88 Document Number: 001-52040 Rev. *A Page 21 of 22 Package Diagram Figure 16. 48-Pin SSOP (51-85061) 51-85061-*C [+] Feedback
Page 22 - Document History Page; Worldwide Sales and Design Support; Rev
Document Number: 001-52040 Rev. *A Revised March 17, 2009 Page 22 of 22 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respectiveholders. STK17T88 © Cypress Semiconduct...