Cypress CY7C1380C - Manual
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Table of Contents:
- Page 3 – Pin Configurations
- Page 5 – TMS
- Page 12 – Functional Overview; Single Read Accesses
- Page 13 – Sleep Mode; Interleaved Burst Address Table; DD; ZZ Mode Electrical Characteristics
- Page 14 – Truth Table for Read/Write
- Page 15 – Disabling the JTAG Feature; ) to prevent clocking of the device. TDI and TMS are; TAP Controller State Diagram; Performing a TAP Reset
- Page 16 – Bypass Register; ) when the BYPASS instruction is executed.; Boundary Scan Register; Overview
- Page 17 – BYPASS; TAP Timing; Over the operating Range; Test Clock
- Page 18 – V TAP AC Output Load Equivalent; TDO; TAP DC Electrical Characteristics And Operating Conditions
- Page 20 – 19-Ball BGA Boundary Scan Order; BALL ID
- Page 22 – 65-Ball fBGA Boundary Scan Order
- Page 24 – Electrical Characteristics
- Page 25 – Thermal Resistance
- Page 26 – AC Test Loads and Waveforms
- Page 27 – Switching Characteristics
- Page 28 – Switching Waveforms; Read Cycle Timing
- Page 29 – Write Cycle Timing
- Page 30 – Read/Write Cycle Timing
- Page 31 – ZZ Mode Timing; CLK
- Page 32 – Ordering Information; Commercial
- Page 33 – Package Diagrams
- Page 36 – Document History Page; Issue Date
18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C
CY7C1382C
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Document #: 38-05237 Rev. *D
Revised February 26, 2004
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 225, 200,166 and
133MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 166-MHz device)
— 4.2 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
•
User-selectable burst counter supporting Intel
®
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
1
), depth-expansion Chip
Enables (CE
2
and
CE
3
[2]
), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW
X
, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1380C/CY7C1382C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
225 MHz
200 MHz
167 MHz
133 MHz
Unit
Maximum Access Time
2.6
2.8
3.0
3.4
4.2
ns
Maximum Operating Current
350
325
300
275
245
mA
Maximum CMOS Standby Current
70
70
70
70
70
mA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
, CE
2
are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
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Summary
CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 3 of 36 Pin Configurations A A A A A 1 A 0 NC / 72M NC / 36M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C...
CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 5 of 36 Pin Configurations (continued) 165-ball fBGA CY7C1380C (512K x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC / 288M NC DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D NC / 36M...
CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 12 of 36 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock.Maximum access delay from the clo...
