Cypress CY7C1380C - Manuals

Cypress CY7C1380C – Manual in PDF format online.

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Manual

Manual Cypress CY7C1380C

Summary

Page 3 - Pin Configurations

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 3 of 36 Pin Configurations A A A A A 1 A 0 NC / 72M NC / 36M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C...

Page 5 - TMS

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 5 of 36 Pin Configurations (continued) 165-ball fBGA CY7C1380C (512K x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC / 288M NC DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D NC / 36M...

Page 12 - Functional Overview; Single Read Accesses

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 12 of 36 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock.Maximum access delay from the clo...

Page 13 - Sleep Mode; Interleaved Burst Address Table; DD; ZZ Mode Electrical Characteristics

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 13 of 36 Asserting ADV LOW at clock rise will automatically incrementthe burst counter to the next address in the burst sequence.Both Read and Write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting Z...

Page 14 - Truth Table for Read/Write

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 14 of 36 READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q R...

Page 15 - Disabling the JTAG Feature; ) to prevent clocking of the device. TDI and TMS are; TAP Controller State Diagram; Performing a TAP Reset

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 15 of 36 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380C incorporates a serial boundary scan testaccess port (TAP). This port operates in accordance with IEEEStandard 1149.1-1990 but does not have the set of functionsrequired for full 1149....

Page 16 - Bypass Register; ) when the BYPASS instruction is executed.; Boundary Scan Register; Overview

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 16 of 36 TDI and TDO balls as shown in the Tap Controller BlockDiagram. Upon power-up, the instruction register is loadedwith the IDCODE instruction. It is also loaded with the IDCODEinstruction if the controller is placed in a reset state asdesc...

Page 17 - BYPASS; TAP Timing; Over the operating Range; Test Clock

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 17 of 36 Note that since the PRELOAD part of the command is notimplemented, putting the TAP to the Update-DR state whileperforming a SAMPLE/PRELOAD instruction will have thesame effect as the Pause-DR command. BYPASS When the BYPASS instruction i...

Page 18 - V TAP AC Output Load Equivalent; TDO; TAP DC Electrical Characteristics And Operating Conditions

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 18 of 36 3.3V TAP AC Test Conditions Input pulse levels ........ ........................................V SS to 3.3V Input rise and fall times ...................... ..............................1ns Input timing reference levels ..................

Page 20 - 19-Ball BGA Boundary Scan Order; BALL ID

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 20 of 36 119-Ball BGA Boundary Scan Order CY7C1380C (512K x 36) BIT# BALL ID BIT# BALL ID 1 K4 37 B2 2 H4 38 P4 3 M4 39 N4 4 F4 40 R6 5 B4 41 T5 6 A4 42 T3 7 G4 43 R2 8 C6 44 R3 9 A6 45 P2 10 D6 46 P1 11 D7 47 N2 12 E6 48 L2 13 G6 49 K1 14 H7 50 ...

Page 22 - 65-Ball fBGA Boundary Scan Order

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 22 of 36 165-Ball fBGA Boundary Scan Order CY7C1380C (512K x 36) BIT# BALL ID BIT# BALL ID 1 B6 37 N6 2 B7 38 R6 3 A7 39 P6 4 B8 40 R4 5 A8 41 R3 6 B9 42 P4 7 A9 43 P3 8 B10 44 R1 9 A10 45 N1 10 C11 46 L2 11 E10 47 K2 12 F10 48 J2 13 G10 49 M2 14...

Page 24 - Electrical Characteristics

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 24 of 36 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature withPower Applied ...............................

Page 25 - Thermal Resistance

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 25 of 36 I SB3 Automatic CE Power-down Current—CMOS Inputs V DD = Max, Device Deselected, or V IN ≤ 0.3V or V IN > V DDQ – 0.3V f = f MAX = 1/t CYC 4.0-ns cycle, 250 MHz 105 mA 4.4-ns cycle, 225 MHz 100 mA 5.0-ns cycle, 200 MHz 95 mA 6.0-ns cy...

Page 26 - AC Test Loads and Waveforms

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 26 of 36 AC Test Loads and Waveforms OUTPUT R = 317 Ω R = 351 Ω 5 pF INCLUDING JIG AND SCOPE (a) (b) OUTPUT R L = 50 Ω Z 0 = 50 Ω V L = 1.5V 3.3V ALL INPUT PULSES V DD GND 90% 10% 90% 10% ≤ 1ns ≤ 1ns (c) OUTPUT R = 1667 Ω R =1538 Ω 5 pF INCLUDING...

Page 27 - Switching Characteristics

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 27 of 36 Switching Characteristics Over the Operating Range [19, 20] Parameter Description 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit Min. Max Min. Max Min. Max t POWER V DD (Typical) to the first Access [15] 1 1 1 1 1 ms Clock t CYC Clock Cycl...

Page 28 - Switching Waveforms; Read Cycle Timing

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 28 of 36 Switching Waveforms Read Cycle Timing [21] Notes: 21. On this diagram, when CE is LOW: CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 22. Full width write can be initiated by eith...

Page 29 - Write Cycle Timing

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 29 of 36 Write Cycle Timing [21, 22] Switching Waveforms (continued) t CYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BW X Data Out (Q) High-Z ADV BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1)...

Page 30 - Read/Write Cycle Timing

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 30 of 36 Read/Write Cycle Timing [21, 23, 24] Note: 23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 24. GW is HIGH. Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS...

Page 31 - ZZ Mode Timing; CLK

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 31 of 36 Notes: 25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.26. DQs are in high-Z when exiting ZZ sleep mode Switching Waveforms (continued) ZZ Mode T...

Page 32 - Ordering Information; Commercial

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 32 of 36 Ordering Information Speed (MHz) Ordering Code Package Name Part and Package Type Operating Range 250 CY7C1380C-250ACCY7C1382C-250AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial CY7C1380C-250BGCCY7C1382C-250BGC BG119 11...

Page 33 - Package Diagrams

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 33 of 36 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a C...

Page 36 - Document History Page; Issue Date

CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 36 of 36 Document History Page Document Title: CY7C1380C/CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAMDocument Number: 38-05237 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 116277 08/27/02 SKX New Data Sheet *A 121540 11/...