Cypress CY7C1314BV18 - Manual
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Table of Contents:
- Page 2 – DOFF; DOFF
- Page 3 – Array
- Page 4 – Pin Configuration
- Page 6 – Pin Definitions; Application Example
- Page 8 – Functional Overview; Write Operations
- Page 9 – Programmable Impedance; to allow the SRAM to adjust its output; Echo Clocks; Switching Characteristics; DLL; AN5062, DLL Considerations in; Figure 1; Figure 1. Application Example; ohms; BUS
- Page 12 – Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set
- Page 13 – and t; ). The SRAM clock input might not be captured
- Page 14 – TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET
- Page 16 – Figure 2
- Page 18 – Boundary Scan Order; Bump ID; Internal
- Page 19 – Power Up Sequence in QDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms
- Page 20 – Maximum Ratings; Operating Range; DC Electrical Characteristics
- Page 21 – AC Electrical Characteristics
- Page 22 – Capacitance; Thermal Resistance
- Page 24 – Switching Waveforms; RPS
- Page 25 – Ordering Information; for actual products offered.
- Page 27 – Package Diagram
- Page 28 – Document History Page; Submission
18-Mbit QDR™-II SRAM 2-Word
Burst Architecture
CY7C1310BV18, CY7C1910BV18
CY7C1312BV18, CY7C1314BV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05619 Rev. *F
Revised June 2, 2008
Features
■
Separate independent read and write data ports
❐
Supports concurrent transactions
■
250 MHz clock for high bandwidth
■
2-word burst on all accesses
■
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 500 MHz) at 250 MHz
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Single multiplexed address input bus latches address inputs
for both read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self-timed writes
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency, providing most current data
■
Core V
DD
= 1.8V (±0.1V); IO V
DDQ
= 1.4V to V
DD
■
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
Variable drive HSTL output buffers
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310BV18 – 2M x 8
CY7C1910BV18 – 2M x 9
CY7C1312BV18 – 1M x 18
CY7C1314BV18 – 512K x 36
Functional Description
The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and
CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has data outputs to
support read operations and the write port has data inputs to
support write operations. QDR-II architecture has separate data
inputs and data outputs to completely eliminate the need to
“turn-around” the data bus required with common IO devices.
Access to each port is accomplished through a common address
bus. The read address is latched on the rising edge of the K clock
and the write address is latched on the rising edge of the K clock.
Accesses to the QDR-II read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are provided with DDR interfaces. Each
address location is associated with two 8-bit words
(CY7C1310BV18), 9-bit words (CY7C1910BV18), 18-bit words
(CY7C1312BV18), or 36-bit words (CY7C1314BV18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K and C and C), memory bandwidth is maximized
while simplifying system design by eliminating bus
“turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
250
200
167
MHz
Maximum Operating Current
x8
735
630
550
mA
x9
735
630
550
x18
800
675
600
x36
900
750
650
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Summary
CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 2 of 29 Logic Block Diagram (CY7C1310BV18) Logic Block Diagram (CY7C1910BV18) 1M x 8 A rray CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add . Decode Read Data Reg. RPS WPS Control Logic Addre...
CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 3 of 29 Logic Block Diagram (CY7C1312BV18) Logic Block Diagram (CY7C1314BV18) 512 K x 18 Array CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add . Decode Read Data Reg. RPS WPS Control Logic A...
CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 4 of 29 Pin Configuration The pin configuration for CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and CY7C1314BV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1310BV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ...
