Cypress CY7C1363C - Manuals

Cypress CY7C1363C – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1363C

Summary

Page 3 - Pin Configurations

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 3 of 31 Pin Configurations A A A A A 1 A 0 NC NC V SS V DD NC A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQ C...

Page 6 - TMS

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 6 of 31 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1361C (256K x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C DQ D DQ D MODE NC DQ C DQ...

Page 7 - Pin Definitions

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 7 of 31 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 [2] are samp...

Page 9 - Functional Overview; Burst Sequences

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 9 of 31 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. Maximum access delay fromthe clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1361C/CY7C1363C supports secondary cach...

Page 12 - Disabling the JTAG Feature; through a pull-up resistor. TDO should be; TAP Controller State Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers; Instruction Register

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 12 of 31 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1361C/CY7C1363C incorporates a serial boundaryscan test access port (TAP) in the BGA package only. TheTQFP package does not offer this functionality. This partoperates in accordance with IEE...

Page 13 - ) when the BYPASS instruction is executed.; TAP Instruction Set; and t

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 13 of 31 TDI and TDO balls as shown in the Tap Controller BlockDiagram. Upon power-up, the instruction register is loadedwith the IDCODE instruction. It is also loaded with the IDCODEinstruction if the controller is placed in a reset state asdescr...

Page 14 - TAP Timing; Test Clock

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 14 of 31 PRELOAD allows an initial data pattern to be placed at thelatched parallel outputs of the boundary scan register cellsprior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phasesca...

Page 16 - Scan Register Sizes; Register Name; Identification Codes; Instruction

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 16 of 31 Scan Register Sizes Register Name Bit Size (x 36) Bit Size (x 18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 71 71 Boundary Scan Order (165-ball FBGA package) 71 71 Identification Codes Instruction Code...

Page 17 - 19-Ball BGA Boundary Scan Order

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 17 of 31 119-Ball BGA Boundary Scan Order CY7C1361C (256K x 36) CY7C1363C (512K x 18) Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name 1 K4 CLK 37 P4 A0 1 K4 CLK 37 P4 A0 2 H4 GW 38 N4 A1 2 H4...

Page 18 - 65-Ball FBGA Boundary Scan Order

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 18 of 31 165-Ball FBGA Boundary Scan Order CY7C1361C (256K x 36) CY7C1363C (512K x 18) Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name 1 B6 CLK 37 R6 A0 1 B6 CLK 37 R6 A0 2 B7 GW 38 P6 A1 2 B...

Page 19 - Electrical Characteristics

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 19 of 31 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature withPower Applied ....................................

Page 20 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 20 of 31 Capacitance [15] Parameter Description Test Conditions 100 TQFP Max. 119 BGA Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5 5 5 pF C CLK Clock Input Capacitance 5 5 5 pF C I/O Input/Outp...

Page 21 - Switching Characteristics

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 21 of 31 Switching Characteristics Over the Operating Range [20, 21] Parameter Description –133 –100 Unit Min. Max. Min. Max. t POWER V DD (Typical) to the first Access [16] 1 1 ms Clock t CYC Clock Cycle Time 7.5 10 ns t CH Clock HIGH 3.0 4.0 ns ...

Page 22 - Timing Diagrams; Read Cycle Timing

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 22 of 31 Timing Diagrams Read Cycle Timing [22] Note: 22. On this diagram, when CE is LOW: CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 t C...

Page 23 - Write Cycle Timing

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 23 of 31 Write Cycle Timing [22, 23] Note: 23. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW X LOW. Timing Diagrams (continued) tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES High-Z BURST READ BURST W...

Page 24 - Read/Write Cycle Timing

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 24 of 31 Read/Write Cycle Timing [22, 24, 25] Notes: 24. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.25. GW is HIGH. Timing Diagrams (continued) tCYC t CL CLK tADH tADS ADDRESS ...

Page 25 - ZZ Mode Timing; CLK

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 25 of 31 ZZ Mode Timing [26, 27] Notes: 26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.27. DQs are in high-Z when exiting ZZ sleep mode. Timing Diagrams (...

Page 26 - Ordering Information; Commercial

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 26 of 31 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part a...

Page 28 - Package Diagrams

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 28 of 31 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS...

Page 31 - Document History Page; Issue Date

CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 31 of 31 Document History Page Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAMDocument Number: 38-05541 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 241690 See ECN RKF New data sheet *A 278969...