Cypress CY7C1372D - Manual
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Table of Contents:
- Page 2 – Selection Guide; Unit
- Page 3 – Pin Configurations
- Page 5 – TMS; 65-Ball FBGA Pinout
- Page 6 – Pin Definitions
- Page 7 – Introduction
- Page 8 – ZZ Mode Electrical Characteristics
- Page 9 – Truth Table
- Page 10 – Partial Write Cycle Description
- Page 11 – Disabling the JTAG Feature; through a pull-up resistor. TDO should be; TAP Controller State Diagram; Performing a TAP Reset; A Reset is performed by forcing TMS HIGH (V; TAP Registers; Instruction Register
- Page 12 – ) when the BYPASS instruction is executed.; TAP Instruction Set; and t
- Page 13 – Reserved; TAP Timing; Test Clock
- Page 14 – TDO; TAP DC Electrical Characteristics And Operating Conditions; Parameter
- Page 16 – 19-Ball BGA Boundary Scan Order; Ball ID; Internal
- Page 17 – 65-Ball BGA Boundary Scan Order
- Page 18 – Electrical Characteristics
- Page 19 – Capacitance; Thermal Resistance; AC Test Loads and Waveforms
- Page 20 – Switching Characteristics
- Page 21 – Switching Waveforms
- Page 23 – Ordering Information; Commercial
- Page 24 – visit
- Page 25 – Package Diagrams
- Page 28 – Document History Page; Issue Date
18-Mbit (512K x 36/1M x 18) Pipelined
SRAM with NoBL™ Architecture
CY7C1370D
CY7C1372D
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05555 Rev. *F
Revised June 28, 2006
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 3.3V core power supply (V
DD
)
• 3.3V/2.5V I/O power supply(V
DDQ
)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in JEDEC-standard lead-free 100-pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and
1M x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL
™)
logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1370D and CY7C1372D are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1370D and CY7C1372D are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
a
–BW
d
for CY7C1370D and BW
a
–BW
b
for CY7C1372D)
and a Write Enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram-CY7C1370D (512K x 36)
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Summary
CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 2 of 28 Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 2.6 3.0 3.4 ns Maximum Operating Current 350 300 275 mA Maximum CMOS Standby Current 70 70 70 mA A0, A1, A C MODE BW a BW b WE CE1CE2CE3 OE READ LOGIC DQsDQP a DQP b D A T A ...
CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQaDQa V DDQ V SS DQaDQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQdDQdDQd V SS V DDQ A A CE ...
CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 5 of 28 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/36M NC/72M V DDQ BW d BW a CLK WE V SS ...
