Cypress CY7C1372D - Manuals

Cypress CY7C1372D – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1372D

Summary

Page 2 - Selection Guide; Unit

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 2 of 28 Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 2.6 3.0 3.4 ns Maximum Operating Current 350 300 275 mA Maximum CMOS Standby Current 70 70 70 mA A0, A1, A C MODE BW a BW b WE CE1CE2CE3 OE READ LOGIC DQsDQP a DQP b D A T A ...

Page 3 - Pin Configurations

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQaDQa V DDQ V SS DQaDQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQdDQdDQd V SS V DDQ A A CE ...

Page 5 - TMS; 65-Ball FBGA Pinout

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 5 of 28 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/36M NC/72M V DDQ BW d BW a CLK WE V SS ...

Page 6 - Pin Definitions

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 6 of 28 Pin Definitions Pin Name I/O Type Pin Description A0A1A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK. BW a BW b BW c BW d Input- Synchronous Byte Write Select Inputs,...

Page 7 - Introduction

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 7 of 28 Introduction Functional Overview The CY7C1370D and CY7C1372D are synchronous-pipelinedBurst NoBL SRAMs designed specifically to eliminate waitstates during Write/Read transitions. All synchronous inputspass through input registers controll...

Page 8 - ZZ Mode Electrical Characteristics

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 8 of 28 Asserting the Write Enable input (WE) with the selected ByteWrite Select (BW) input will selectively write to only the desiredbytes. Bytes not selected during a byte write operation willremain unaltered. A synchronous self-timed write mech...

Page 9 - Truth Table

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 9 of 28 Notes: 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write...

Page 10 - Partial Write Cycle Description

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 10 of 28 Partial Write Cycle Description [1, 2, 3, 8] Function (CY7C1370D) WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ a and DQP a ) L H H H L Write Byte b – (DQ b and DQP b ) L H H L H Write Bytes b...

Page 11 - Disabling the JTAG Feature; through a pull-up resistor. TDO should be; TAP Controller State Diagram; Performing a TAP Reset; A Reset is performed by forcing TMS HIGH (V; TAP Registers; Instruction Register

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 11 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370D/CY7C1372D incorporates a serial boundaryscan test access port (TAP). This part is fully compliant with1149.1. The TAP operates using JEDEC-standard 3.3V or2.5V I/O logic levels. The CY...

Page 12 - ) when the BYPASS instruction is executed.; TAP Instruction Set; and t

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 12 of 28 When the TAP controller is in the Capture-IR state, the twoleast significant bits are loaded with a binary “01” pattern toallow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shift...

Page 13 - Reserved; TAP Timing; Test Clock

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 13 of 28 in the TAP controller, it will directly control the state of theoutput (Q-bus) pins, when the EXTEST is entered as thecurrent instruction. When HIGH, it will enable the outputbuffers to drive the output bus. When LOW, this bit will placet...

Page 14 - TDO; TAP DC Electrical Characteristics And Operating Conditions; Parameter

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 14 of 28 3.3V TAP AC Test Conditions Input pulse levels ................................................ V SS to 3.3V Input rise and fall times ................................................... 1 ns Input timing reference levels ...................

Page 16 - 19-Ball BGA Boundary Scan Order; Ball ID; Internal

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 16 of 28 119-Ball BGA Boundary Scan Order [13, 14] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 L5 28 E6 50 B3 72 L2 7 ...

Page 17 - 65-Ball BGA Boundary Scan Order

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 17 of 28 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C...

Page 18 - Electrical Characteristics

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 18 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ....................................

Page 19 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 19 of 28 Note: 18. Tested initially and after any design or process change that may affect these parameters. Capacitance [18] Parameter Description Test Conditions 100 TQFP Max. 119 BGA Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25 ° C, ...

Page 20 - Switching Characteristics

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 20 of 28 Switching Characteristics Over the Operating Range [23, 24] Parameter Description –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [19] V CC (typical) to the first access read or write 1 1 1 ms Clock t CYC Clock Cycle Time 4.0 5 ...

Page 21 - Switching Waveforms

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 21 of 28 Switching Waveforms Read/Write/Timing [25, 26, 27] Notes: 25. For this waveform ZZ is tied LOW.26. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH,CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 27. Order of the Bu...

Page 23 - Ordering Information; Commercial

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 23 of 28 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part a...

Page 24 - visit

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 24 of 28 250 CY7C1370D-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1372D-250AXC CY7C1370D-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372D-250BGC CY7C1370D-250BGXC 51-85115 119-ball ...

Page 25 - Package Diagrams

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 25 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS...

Page 28 - Document History Page; Issue Date

CY7C1370DCY7C1372D Document #: 38-05555 Rev. *F Page 28 of 28 Document History Page Document Title: CY7C1372D/CY7C1370D 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ ArchitectureDocument Number: 38-05555 REV. ECN No. Issue Date Orig. of Change Description of Change ** 254509 See ECN RKF New ...