Cypress CY7C68023 - Manual
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Table of Contents:
- Page 2 – Pin Assignments; Pin Diagram; Pin
- Page 3 – Pin Descriptions
- Page 4 – Additional Pin Descriptions; CLE
- Page 5 – Applications; Mass Storage Class Bulk Only Transport; Functional Overview
- Page 6 – Table 6-1. Variable Configuration Data And Default ROM Values
- Page 7 – AC Electrical Characteristics; USB Transceiver; Ordering Information; DC Characteristics
- Page 8 – Package Diagram
- Page 9 – Document History Page; Issue
EZ-USB NX2LP™ USB 2.0 NAND
Flash Controller
CY7C68023/CY7C68024
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-08055 Rev. *B
Revised October 5, 2005
1.0
Features
• High (480-Mbps) or full (12-Mbps) speed USB support
• Both common NAND page sizes supported
— 512bytes—Up to 1 Gbit Capacity
— 2K bytes—Up to 8 Gbit Capacity
• 8 chip enable pins
— Up to 8 NAND Flash single-device chips
— Up to 4 NAND Flash dual-device chips
• Industry standard ECC NAND Flash correction
— 1 bit per 256 correction
— 2 bit error detection
• Industry standard (SmartMedia) page management for
wear leveling algorithm, bad block handling, and
Physical to Logical management.
• Supports 8-bit NAND Flash interfaces
• Supports 30-ns, 50-ns, 100-ns NAND Flash timing
• Complies with USB Mass Storage Class Specification
rev 1.0
• CY7C68024 complies with USB 2.0 Specification for
Bus-Powered Devices (TID# 40460274)
• 43-mA Typical Active Current
•
Space-saving and lead-free 56-QFN package (8 mm
×
8 mm)
• Support for board-level manufacturing test via USB
interface
• 3.3V NAND Flash operation
• NAND Flash power management support
2.0
The EZ-USB NX2LP
(
NX2LP
)
implements a USB 2.0 NAND
Flash controller. This controller adheres to the
Mass Storage
Class Bulk-Only Transport
Specification
. The USB port of the
NX2LP is connected to a host computer directly or via the
downstream port of a USB hub. Host software issues
commands and data to the NX2LP and receives status and
data from the NX2LP using standard USB protocol.
The NX2LP supports industry leading 8-bit NAND Flash inter-
faces and both common NAND page sizes of 512 and 2k
bytes. Eight chip enable pins allow the NX2LP to be connected
to up to eight single- or four dual-device NAND Flash chips.
Certain NX2LP features are configurable, enabling the NX2LP
to meet the needs of different designs’ requirements.
Figure 1-1. NX2LP Block Diagram
USB 2.0
Xceiver
Smart HS/
FS USB
Engine
NAND Flash
Interface
Logic
8-bit Data Bus
NAND Control Signals
EZ-USB NX2LP
Internal Control Logic
PLL
24 MHz
Xtal
VBUS
D+
D-
Data
Control
Chip Reset
LED1#
LED2#
Write Protect
Chip Enable Signals
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Summary
CY7C68023/CY7C68024 Document #: 38-08055 Rev. *B Page 2 of 9 3.0 Pin Assignments 3.1 Pin Diagram Figure 3-1. 56-pin QFN 3.2 Pin Descriptions Pin Name Type Default State at Start-up Description 1 R_B1# [1] I Z Ready/Busy 1 (2.2k to 4k pull-up resistor is required) 2 R_B2# I Z Ready/Busy 2 (2.2k to 4k...
CY7C68023/CY7C68024 Document #: 38-08055 Rev. *B Page 3 of 9 16 Reserved N/A N/A Must be tied HIGH (no pull-up resistor required) 17 VCC PWR PWR 3.3V supply 18 DDO I/O Z Data 0 19 DD1 I/O Z Data 1 20 DD2 I/O Z Data 2 21 DD3 I/O Z Data 3 22 DD4 I/O Z Data 4 23 DD5 I/O Z Data 5 24 DD6 I/O Z Data 6 25 ...
CY7C68023/CY7C68024 Document #: 38-08055 Rev. *B Page 4 of 9 3.3 Additional Pin Descriptions 3.3.1 DPLUS, DMINUS DPLUS and DMINUS are the USB signaling pins, and they should be tied to the D+ and D– pins of the USB connector. Because they operate at high frequencies, the USB signals require special ...
