Cypress CY7C1145V18 - Manual
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Table of Contents:
- Page 3 – DOFF
- Page 4 – Pin Configurations
- Page 6 – Pin Definitions; “Switching Characteristics”
- Page 8 – Functional Overview; Read Operations; Write Operations; Concurrent Transactions
- Page 9 – to enable the SRAM to adjust its output; Echo Clocks; synchronized to the input; DLL
- Page 10 – Application Example; Figure 1; Truth Table; BUS MASTER
- Page 11 – Write Cycle Descriptions
- Page 13 – Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register
- Page 14 – and t; ). The SRAM clock input might not be captured
- Page 15 – TAP Controller State Diagram; Figure 2. Tap Controller State Diagram
- Page 19 – Boundary Scan Order; Bump ID; Internal
- Page 20 – Figure 5. Power Up Waveforms; Unstable Clock
- Page 21 – Electrical Characteristics
- Page 22 – ZQ
- Page 23 – Switching Characteristics
- Page 24 – Switching Waveforms; Figure 7. Waveform for 2.0 Cycle Read Latency
- Page 25 – Ordering Information; for actual products offered.
- Page 27 – Package Diagram
- Page 28 – Document History Page; Issue Date
CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
18-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-06583 Rev. *D
Revised March 06, 2008
Features
■
Separate Independent read and write data ports
❐
Supports concurrent transactions
■
300 MHz to 375 MHz clock for high bandwidth
■
4-Word Burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 750 MHz) at 375 MHz
■
Read latency of 2.0 clock cycles
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■
Single multiplexed address input bus latches address inputs
for both read and write ports
■
Separate Port Selects for depth expansion
■
Data valid pin (QVLD) to indicate valid data on the output
■
Synchronous internally self-timed writes
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency providing most current data
■
Core V
DD
= 1.8V ± 0.1V; IO V
DDQ
= 1.4V to V
DD
■
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
Variable drive HSTL output buffers
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1141V18 – 2M x 8
CY7C1156V18 – 2M x 9
CY7C1143V18 – 1M x 18
CY7C1145V18 – 512K x 36
Functional Description
The CY7C1141V18, CY7C1156V18, CY7C1143V18, and
CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II+ architecture. QDR-II+ architecture
consists of two separate ports to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common IO devices. Access to each
port is accomplished through a common address bus.
Addresses for read and write addresses are latched on alternate
rising edges of the input (K) clock. Accesses to the QDR-II+ read
and write ports are completely independent of one another. To
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1141V18), or 9-bit words (CY7C1156V18), or 18-bit words
(CY7C1143V18), or 36-bit words (CY7C1145V18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks K and K, memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each port.
Port Selects enable each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description
375 MHz
333 MHz
300 MHz
Unit
Maximum Operating Frequency
375
333
300
MHz
Maximum Operating Current
1020
920
850
mA
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V
DDQ
= 1.4V to V
DD
.
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Summary
CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18 Document Number: 001-06583 Rev. *D Page 3 of 28 Logic Block Diagram (CY7C1143V18) Logic Block Diagram (CY7C1145V18) 256K x 1 8 Arra y CLK A (17:0) Gen. K K Control Logic Address Register D [17:0] R ead Add. D e code Read Data Reg. RPS WPS Q [17:0] Con...
CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18 Document Number: 001-06583 Rev. *D Page 4 of 28 Pin Configurations CY7C1141V18 (2M x 8) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 2 3 4 5 6 7 1 A BCD E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A NWS 1 K WPS NC/144M NC NC NC NC NC TDO NC NC D5...
CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18 Document Number: 001-06583 Rev. *D Page 6 of 28 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1141V18 − D [7:0] CY7C1156V18 − ...
