Cypress STK17T88 - Manual
Cypress STK17T88 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Pin Configurations; Pin Descriptions
- Page 3 – Absolute Maximum Ratings; DC Characteristics; STORE
- Page 4 – AC Test Conditions; Figure 2; Capacitance
- Page 5 – RTC DC Characteristics; RF
- Page 8 – AutoStore/Power Up RECALL; RECALL
- Page 10 – Hardware STORE to SRAM Disabled; Hardware STORE Pulse Width; Soft Sequence Processing Time
- Page 11 – MODE Selection; Mode
- Page 12 – nvSRAM Operation; SRAM READ; Figure 13. AutoStore Mode; SRAM WRITE; istics
- Page 13 – Stopping and Starting the RTC Oscillator
- Page 14 – Real Time Clock; Reading the Clock; Setting; Calibrating The Clock; Capacitor Value
- Page 15 – Alarm; Watchdog Timer; Interrupts
- Page 16 – is a functional diagram of the interrupt logic.; Figure 15. Interrupt Block Diagram; Interrupt Register; . When set to a 0, the INT pin is active low; Flags Register
- Page 17 – RTC Register Map; Register
- Page 18 – Register Map Detail
- Page 20 – Ordering Codes
- Page 21 – Package Diagram
- Page 22 – Document History Page; Worldwide Sales and Design Support; Rev
STK17T88
32K x 8 AutoStore™ nvSRAM with
Real Time Clock
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
• 408-943-2600
Document Number: 001-52040 Rev. *A
Revised March 17, 2009
Features
■
nvSRAM Combined With Integrated Real-Time Clock
Functions (RTC, Watchdog Timer, Clock Alarm, Power
Monitor)
■
Capacitor or Battery Backup for RTC
■
25, 45 ns Read Access and R/W Cycle Time
■
Unlimited Read/Write Endurance
■
Automatic Nonvolatile STORE on Power Loss
■
Nonvolatile STORE Under Hardware or Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited RECALL Cycles
■
200K STORE Cycles
■
20-Year Nonvolatile Data Retention
■
Single 3V +20%, -10% Power Supply
■
Commercial and Industrial Temperatures
■
48-pin 300-mil SSOP Package (RoHS-Compliant)
Description
The Cypress STK17T88 combines a 256 Kb nonvolatile static
RAM (nvSRAM) with a full-featured real-time clock in a reliable,
monolithic integrated circuit.
The 256 Kb nvSRAM is a fast static RAM with a nonvolatile
Quantum Trap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the
STORE
operation). On power up,
data is automatically restored to the SRAM (the
RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-time alarms or periodic
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
ROW
D
E
CO
DER
IN
PU
T BU
FFER
S
COLUMN DEC
G
E
W
COLUMN I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
A
13
– A
0
STORE
RECALL
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
V
CC
V
CAP
RTC
MUX
A
14
– A
0
X
1
X
2
INT
V
RTCbat
V
RTCcap
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
A
0
A
1
A
2
A
3
A
4
A
10
Quantum Trap
512 X 512
STATIC RAM
ARRAY
512 X 512
Logic Block Diagram
"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.
Summary
STK17T88 Document Number: 001-52040 Rev. *A Page 2 of 22 Pin Configurations Figure 1. 48-Pin SSOP V SS A 14 A 12 A 7 A 6 DQ 0 DQ 1 V CC DQ 2 A 3 A 2 A 1 V CAP A 13 A 6 A 9 A 11 A 10 DQ 7 DQ 6 V SS A 0 NC 4443424140393837363534333231302928272625 1 2345678910111213141516171819202122 NC E X 1 X 2 2324 ...
STK17T88 Document Number: 001-52040 Rev. *A Page 3 of 22 Absolute Maximum Ratings Voltage on Input Relative to Ground................. –0.5V to 4.1V Voltage on Input Relative to V SS ...........–0.5V to (V CC + 0.5V) Voltage on DQ 0-7 or HSB ......................–0.5V to (V CC + 0.5V) Temperature u...
STK17T88 Document Number: 001-52040 Rev. *A Page 4 of 22 AC Test Conditions Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times ...................................................≤ 5ns Input and Output Timing Reference Levels ......................
