Cypress CY7C602xx - Manual

Cypress CY7C602xx

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Table of Contents:

  • Page 3 – Top View
  • Page 7 – Note; b = Both Read and Write; Table 7-1. enCoRe II LV Register Summary
  • Page 10 – Addressing Modes
  • Page 12 – Instruction Set Summary; PSoC Designer Assembly Language User Guide
  • Page 14 – Memory Organization; Flash Program Memory Organization; Figure 11-1. Program Memory Space with Interrupt Vector Table
  • Page 15 – Data Memory Organization; parameter block; Stack begins here and grows upward
  • Page 16 – SROM Function Descriptions
  • Page 17 – Clocking
  • Page 19 – SROM Table Read Description; SROM
  • Page 20 – BLOCKID
  • Page 21 – Trim Values for the IOSCTR Register; SROM Table Read Description; Supervisory ROM Table
  • Page 22 – Clock Architecture Description; where
  • Page 23 – Reserved; The CPU speed selection is configured using the OSC_CR0 Register (
  • Page 28 – Resonator
  • Page 29 – CPU Clock During Sleep Mode; When the CPU enters sleep mode the CPUCLK Select (Bit 0,; 2 kHz Low Power; conditions with this setting.
  • Page 30 – Sleep Mode
  • Page 31 – Watchdog Timer Reset
  • Page 33 – Wakeup Sequence
  • Page 34 – Low Voltage Detect Control
  • Page 36 – General Purpose IO Ports; Port Data Registers
  • Page 37 – GPIO Port Configuration; When clear, the corresponding interrupt is disabled on the pin.; The GPIOs default to CMOS threshold. User’s firmware
  • Page 39 – CLK Output; and; follow this procedure:
  • Page 40 – DC Characteristics
  • Page 42 – Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see
  • Page 45 – Important Note for Comm Modes 01b or 10b (SPI Master or SPI Slave)
  • Page 47 – SPI Interface Pins; SCLK
  • Page 48 – Figure 18-2. Time Capture Block Diagram; First Edge Hold
  • Page 52 – Figure 18-3. Timer Functional Sequence Diagram
  • Page 53 – Memory mapped registers Read/Write timing diagram
  • Page 54 – Interrupt Controller; Architectural Description; I n ter r u p t
  • Page 59 – Absolute Maximum Ratings; DC Characteristics
  • Page 60 – AC Characteristics
  • Page 61 – SS
  • Page 63 – Ordering Information; Bake Temperature
  • Page 64 – Package Diagrams
  • Page 67 – Document History Page
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CY7C601xx, CY7C602xx

enCoRe™ II Low Voltage Microcontroller

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document 38-16016 Rev. *E

Revised December 08, 2008

1. Features

■

enCoRe

™

II Low Voltage (enCoRe II LV)—enhanced

component reduction

❐

Internal crystalless oscillator with support for optional exter-
nal clock or external crystal or resonator

❐

Configurable IO for real world interface without external com-
ponents

■

Enhanced 8-bit microcontroller

❐

Harvard architecture

❐

M8C CPU speed up to 12 MHz or sourced by an external
crystal, resonator, or clock signal

■

Internal memory

❐

256 bytes of RAM

❐

8 Kbytes of Flash including EEROM emulation

■

Low power consumption

❐

Typically 2.25 mA at 3 MHz

❐

5

μ

A sleep

■

In-system reprogrammability

❐

Allows easy firmware update

■

General purpose IO ports

❐

Up to 36 General Purpose IO (GPIO) pins

❐

2 mA source current on all GPIO pins. Configurable 8 or
50 mA per pin current sink on designated pins

❐

Each GPIO port supports high impedance inputs, config-
urable pull up, open drain output, CMOS and TTL inputs, and
CMOS output

❐

Maskable interrupts on all IO pins

■

SPI serial communication

❐

Master or slave operation

❐

Configurable up to 2 Mbit per second transfers

❐

Supports half duplex single data line mode for optical sensors

■

2-channel 8-bit or 1-channel 16-bit capture timer registers.
Capture timer registers store both rising and falling edge times

❐

Two registers each for two input pins

❐

Separate registers for rising and falling edge capture

❐

Simplifies interface to RF inputs for wireless applications

■

Internal low power wakeup timer during suspend mode

❐

Periodic wakeup with no external components

■

Programmable interval timer interrupts

■

Reduced RF emissions at 27 MHz and 96 MHz

■

Watchdog timer (WDT)

■

Low voltage detection with user selectable threshold voltages

■

Improved output drivers to reduce EMI

■

Operating voltage from 2.7V to 3.6V DC

■

Operating temperature from 0–70°C

■

Available in 24 and 40-pin PDIP, 24-pin SOIC, 24-pin QSOP
and SSOP, 28-pin SSOP, and 48-pin SSOP

■

Advanced development tools based on Cypress PSoC

®

tools

■

Industry standard programmer support

Internal
12 MHz

Oscillator

Clock

Control

Crystal

Oscillator

CY7C601xx only

POR /

Low-Voltage

Detect

Watchdog

Timer

M8C CPU

16 Extended

I/O Pins

16 GPIO

Pins

Wakeup

Timer

Capture

Timers

12-bit Timer

Vd

d

Interrupt

Control

4 SPI/GPIO

Pins

Flash

8K Byte

RAM

256 Byte

2. Logic Block Diagram

[+] Feedback

[+] Feedback

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Summary

Page 3 - Top View

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 3 of 68 6. Pinouts Figure 6-1. Package Configurations 123456 9 11 15 16 17 18 19 20 2221 NC P0.7 TIO1/P0.6TIO0/P0.5 INT2/P0.4INT1/P0.3 CLKIN\P0.0 P2.0 P1.5/SMOSI P1.3/SSEL P3.1P3.0 V DD P1.2 P1.1P1.0 14 P1.4/SCLK 10 P2.1 NC V SS 12 13 78 INT0/P0.2 ...

Page 7 - Note; b = Both Read and Write; Table 7-1. enCoRe II LV Register Summary

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 7 of 68 Note In the R/W column: b = Both Read and Write r = Read Only w = Write Only c = Read or Clear d = Calibration Value. Must not change during normal use 34 IOSCTR foffset[2:0] Gain[4:0] bbbbbbbb 000ddddd 35 XOSCTR Reserved XOSC XGM [2:0] Res...

Page 10 - Addressing Modes

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 10 of 68 9.2 Addressing Modes 9.2.1 Source Immediate The result of an instruction using this addressing mode is placedin the A register, the F register, the SP register, or the X register,which is specified as part of the instruction opcode. Operan...

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