Cypress CY7C1020BN - Manual
Cypress CY7C1020BN – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Operating Range; CC; Electrical Characteristics
- Page 3 – Parameter
- Page 4 – Switching Waveforms
- Page 6 – ADDRESS
- Page 7 – Package Diagrams
- Page 8 – Document History Page; Description of Change; See ECN
32K x 16 Static RAM
CY7C1020BN
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-06443 Rev. **
Revised February 1, 2006
Features
• High speed
— t
AA
= 12, 15 ns
• CMOS for optimum speed/power
• Low active power
— 825 mW (max.)
• Low CMOS standby power (L version only)
— 2.75 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1020BN is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
9
to I/O
16
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020BN is available in standard 44-pin TSOP Type
II and 400-mil-wide SOJ packages.
WE
Logic Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
SOJ / TSOP II
12
13
41
44
43
42
16
15
29
30
V
CC
A
15
A
14
A
13
A
12
NC
NC
A
3
OE
V
SS
A
5
I/O
16
A
2
CE
I/O
3
I/O
1
I/O
2
BHE
NC
A
1
A
0
18
17
20
19
I/O
4
27
28
25
26
22
21
23
24
NC
V
SS
I/O
7
I/O
5
I/O
6
I/O
8
A
6
A
7
BLE
V
CC
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
A
8
A
9
A
10
A
11
32K x 16
RAM Array
I/O
1
–I/O
8
ROW DECODER
A
7
A
6
A
5
A
4
A
3
A
0
COLUMN DECODER
A
9
A
10
A
11
A
12
A
13
A
14
SENSE AMPS
DATA IN DRIVERS
OE
A
2
A
1
I/O
9
–I/O
16
CE
WE
BLE
BHE
A
8
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Summary
CY7C1020BN Document #: 001-06443 Rev. ** Page 2 of 8 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature withPower Applied .........................................
CY7C1020BN Document #: 001-06443 Rev. ** Page 3 of 8 AC Test Loads and Waveforms Switching Characteristics [5] Over the Operating Range Parameter Description 7C1020BN-12 7C1020BN-15 Unit Min. Max. Min. Max. Read Cycle t RC Read Cycle Time 12 15 ns t AA Address to Data Valid 12 15 ns t OHA Data Hold ...
CY7C1020BN Document #: 001-06443 Rev. ** Page 4 of 8 Switching Waveforms Read Cycle No. 1 [9, 10] Read Cycle No. 2 (OE Controlled) [10, 11] Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = V IL . 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE trans...
