Cypress CY7C2576KV18 - Manual
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Table of Contents:
- Page 2 – PRELIMINARY; DOFF
- Page 3 – Arra
- Page 4 – Pin Configuration
- Page 7 – Switching Characteristics
- Page 8 – Functional Overview; Read Operations; Write Operations; Concurrent Transactions
- Page 9 – Depth Expansion; Echo Clocks; PLL; PLL Considerations
- Page 10 – Application Example; Figure 1; DATA IN
- Page 13 – Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set
- Page 15 – Figure 2. TAP Controller State Diagram; The state diagram for the TAP controller follows.
- Page 16 – TAP Electrical Characteristics
- Page 17 – TAP AC Switching Characteristics; Figure 4
- Page 19 – Table 10. Boundary Scan Order; Internal
- Page 20 – Power Up Sequence; Figure 5. Power Up Waveforms
- Page 21 – Maximum Ratings; DC Electrical Characteristics
- Page 22 – AC Electrical Characteristics; Capacitance
- Page 23 – ZQ
- Page 25 – Switching Waveforms; Figure 6. Waveform for 2.5 Cycle Read Latency; WPS
- Page 26 – Ordering Information
- Page 27 – Commercial
- Page 28 – Package Diagram
- Page 29 – Worldwide Sales and Design Support; Document History Page; Change
72-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency) with ODT
PRELIMINARY
CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-15887 Rev. *E
Revised April 24, 2009
Features
■
Separate independent read and write data ports
❐
Supports concurrent transactions
■
550 MHz clock for high bandwidth
■
4-word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces on both read and write
ports (data transferred at 1100 MHz) at 550 MHz
■
Available in 2.5 clock cycle latency
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Data valid pin (QVLD) to indicate valid data on the output
■
On-Die Termination (ODT) feature
❐
Supported for D
[x:0]
, BWS
[x:0]
, and K/K inputs
■
Single multiplexed address input bus latches address inputs
for read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self-timed writes
■
QDR™-II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■
Operates similar to QDR-I device with 1 cycle read latency
when DOFF is asserted LOW
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency, providing most current data
■
Core V
DD
= 1.8V± 0.1V; IO V
DDQ
= 1.4V to V
DD
❐
Supports both 1.5V and 1.8V IO supply
■
HSTL inputs and variable drive HSTL output buffers
■
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Phase Locked Loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C2561KV18 – 8M x 8
CY7C2576KV18 – 8M x 9
CY7C2563KV18 – 4M x 18
CY7C2565KV18 – 2M x 36
Functional Description
The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and
CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II+ architecture. Similar to QDR-II archi-
tecture, QDR-II+ architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus that exists with common IO devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR-II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C2561KV18), 9-bit words (CY7C2576KV18), 18-bit
words (CY7C2563KV18), or 36-bit words (CY7C2565KV18) that
burst sequentially into or out of the device. Because data is trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
These devices have an On-Die Termination feature supported
for D
[x:0]
, BWS
[x:0]
, and K/K inputs, which helps eliminate
external termination resistors, reduce cost, reduce board area,
and simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Table 1. Selection Guide
Description
550 MHz
500 MHz
450 MHz
400 MHz
Unit
Maximum Operating Frequency
550
500
450
400
MHz
Maximum Operating Current
x8
900
830
760
690
mA
x9
900
830
760
690
x18
920
850
780
710
x36
1310
1210
1100
1000
Note
1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support V
DDQ
= 1.4V to V
DD
.
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About this manual
- Brand
- Cypress
- Model
- CY7C2576KV18
- Document type
- Manual
- Language(s)
- English
- Pages
- 29
- File size
- 840 KB
- Format
Summary
PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 2 of 29 Logic Block Diagram (CY7C2561KV18) Logic Block Diagram (CY7C2576KV18) 2M x 8 A rra y CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Rea d Add. Decode Read Data Reg. RPS WPS ...
PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 3 of 29 Logic Block Diagram (CY7C2563KV18) Logic Block Diagram (CY7C2565KV18) 1M x 18 Array CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add . Decode Read Data Reg. RPS WPS ...
PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 4 of 29 Pin Configuration The pin configuration for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follow. [2] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C2561KV18 (8M x 8) 1 2 3 4 5 ...
