Cypress CY14B101P - Manual - manualsarea.com

Page 2 - PRELIMINARY; Pinouts

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 2 of 32 Pinouts Figure 1. Pin Diagram - 16-Pin SOIC Table 1. Pin Definitions Pin Name I/O Type Description CS Input Chip Select . Activates the device when pulled LOW. Driving this pin HIGH puts the device in low power standby mode. SCK Input ...

Page 3 - Device Operation; SRAM Write; perform infinite; SRAM Read; Figure 2

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 3 of 32 Device Operation CY14B101P is a 1-Mbit nvSRAM memory with integrated RTCand SPI interface. All the reads and writes to nvSRAM happento the SRAM which gives nvSRAM the unique capability tohandle infinite writes to the memory. The data i...

Page 4 - Figure 2. AutoStore Mode; Serial Peripheral Interface

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 4 of 32 Figure 2. AutoStore Mode Software Store Operation Software Store allows the user to trigger a STORE operationthrough a special SPI instruction. This operation is initiatedirrespective of whether a write has been performed since last nv...

Page 5 - The commonly used terms used in SPI protocol are given below:; Note; A new instruction must begin with the falling edge of Chip

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 5 of 32 master is the opcode. Following the opcode, any addresses anddata are then transferred. The CS must go inactive after anoperation is complete and before a new opcode can be issued. The commonly used terms used in SPI protocol are given...

Page 6 - SPI Modes; The two SPI modes are shown in; Figure 3. System Configuration Using SPI nvSRAM; Figure 4. SPI Mode 0; LSB; Figure 5. SPI Mode 3; SCK

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 6 of 32 SPI Modes CY14B101P device may be driven by a microcontroller with itsSPI peripheral running in either of the following two modes: ■ SPI Mode 0 (CPOL=0, CPHA=0) ■ SPI Mode 3 (CPOL=1, CPHA=1) For both these modes, input data is latched ...

Page 7 - SPI Operating Features; Power Up; DC Electrical Characteristics; SPI Functional Description; Table 2

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 7 of 32 SPI Operating Features Power Up Power up is defined as the condition when the power supply isturned on and V CC crosses Vswitch voltage. During this time, the Chip Select (CS) must be enabled to follow the V CC voltage. Therefore, CS m...

Page 8 - Status Register; Table 3

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 8 of 32 Status Register The status register bits are listed in Table 3 . The status register consists of Ready bit (RDY) and data protection bits BP1, BP0, WEN and WPEN. The RDY bit can be polled to check the Ready/Busy status while a nvSRAM S...

Page 9 - Write Protection and Block Protection; Block Protection; segment is read only.; None

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 9 of 32 Write Protection and Block Protection CY14B101P provides features for both software and hardwarewrite protection using WRDI instruction and WP. Additionally, thisdevice also provides block protection mechanism through BP0and BP1 pins o...

Page 10 - Table 6; Memory Access

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 10 of 32 When WP pin is LOW and WPEN is set to “1”, any modificationsto status register are disabled. Therefore, the memory isprotected by setting the BP0 and BP1 bits and the WP pin inhibitsany modification of the status register bits, provid...

Page 11 - Read RTC instruction operates at a maximum clock; Figure 11. Burst Mode Read Instruction Timing

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 11 of 32 READ RTC (RDRTC) Instruction Read RTC (RDRTC) instruction allows the user to read thecontents of RTC registers. Reading the RTC registers throughthe serial output (SO) pin requires the following sequence: Afterthe CS line is pulled LO...

Page 12 - nvSRAM Special Instructions; Table 7; Table 7. nvSRAM Special Instructions

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 12 of 32 WRITE RTC (WRTC) Instruction WRITE RTC (WRTC) instruction allows the user to modify thecontents of RTC registers. The WRTC instruction requires theWEN bit to be set to '1' before it can be issued. If WEN bit is '0',a WREN instruction ...

Page 13 - HOLD Pin Operation; Figure 17. Software RECALL Operation

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 13 of 32 bit is cleared on the positive edge of CS following the STOREinstruction. Software Recall (RECALL) When a RECALL instruction is executed, CY14B101P performsa Software Recall operation. To issue this instruction, the devicemust be writ...

Page 14 - Real Time Clock Operation; Setting the Clock; Table 8. RTC Backup Time

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 14 of 32 Real Time Clock Operation nvTIME Operation The CY14B101P offers internal registers that contain clock,alarm, watchdog, interrupt, and control functions. The RTCregisters occupy a separate address space from nvSRAM andare accessible th...

Page 15 - Calibrating the Clock; Alarm; Watchdog Timer

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 15 of 32 The value of OSCF must be reset to ‘0’ when the time registersare written for the first time. This initializes the state of this bitwhich may have become set when the system was first poweredon. To reset OSCF, set the write bit “W” (i...

Page 16 - Power Monitor; “AutoStore Operation”; Interrupts; Interrupt Register; Watchdog Interrupt Enable - WIE; Flags Register; “Stopping and Starting the Oscillator”; Figure 21. Watchdog Timer Block Diagram

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 16 of 32 . Power Monitor The CY14B101P provides a power management scheme withpower fail interrupt capability. It also controls the internal switchto backup power for the clock and protects the memory from lowV CC access. The power monitor is ...

Page 17 - Accessing the Real Time Clock through SPI; Figure 22. RTC Recommended Component Configuration; WDF - Watchdog Timer Flag

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 17 of 32 Accessing the Real Time Clock through SPI CY14B101P uses 16 registers for Real Time Clock (RTC). Theseregisters can be read out or written to by accessing all 16registers in burst mode or accessing each register, one at a time.The RDR...

Page 18 - Table 9. RTC Register Map

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 18 of 32 Table 9. RTC Register Map [1, 2] Register BCD Format Data Function/Range D7 D6 D5 D4 D3 D2 D1 D0 0x0F 10s Years Years Years: 00–99 0x0E 0 0 0 10s Months Months Months: 01–12 0x0D 0 0 10s Day of Month Day Of Month Day of Month: 01–31 0...

Page 19 - Table 10. Register Map Detail

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 19 of 32 Table 10. Register Map Detail 0x0F Time Keeping - Years D7 D6 D5 D4 D3 D2 D1 D0 10s Years Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains th...

Page 20 - WatchDog Timer; Interrupt Status/Control

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 20 of 32 0x07 WatchDog Timer D7 D6 D5 D4 D3 D2 D1 D0 WDS WDW WDT WDS Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit is cleared automatically after the watchdog timer ...

Page 21 - Time Keeping - Centuries

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 21 of 32 0x02 Alarm - Seconds D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Seconds Alarm Seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value. M Match. When this bit is set to 0, the seconds value i...

Page 22 - Maximum Ratings

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 22 of 32 Maximum Ratings Exceeding maximum ratings may shorten the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Maximum Accumulated Storage Time At 15...

Page 23 - AC Test Conditions; Thermal Resistance; OUTPUT

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 23 of 32 AC Test Conditions Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times (10% - 90%) ........................ <3 ns Input and Output Timing Reference Levels .................... ...

Page 24 - AC Switching Characteristics

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 24 of 32 Table 12. RTC Characteristics Parameters Description Test Conditions Min Typ Max Units I BAK [7] RTC Backup Current Room Temperature (25 o C) 300 nA Hot Temperature (85 o C) 450 nA V RTCbat RTC Battery Pin Voltage 1.8 3.0 3.3 V V RTCc...

Page 25 - Figure 26. HOLD Timing

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 25 of 32 Figure 25. Synchronous Data Timing (Mode 0) Figure 26. HOLD Timing HI-Z VALID IN HI-Z CS SCK SI SO tCL tCH tCSS tSD tHD tCO tOH tCS tCSH tHZCS CS SCK HOLD SO tSH tHHZ tHLZ tHH tSH tHH ~ ~ ~ ~ [+] Feedback

Page 26 - AutoStore or Power Up RECALL; Switching Waveforms

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 26 of 32 AutoStore or Power Up RECALL Parameters Description CY14B101P Unit Min Max t FA [8] Power Up RECALL Duration 20 ms t STORE [9] STORE Cycle Duration 8 ms t DELAY [10] Time Allowed to Complete SRAM Cycle 25 ns V SWITCH Low Voltage Trigg...

Page 27 - Software Controlled STORE/RECALL Cycles; RECALL Duration; Soft Sequence Processing Time

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 27 of 32 Software Controlled STORE/RECALL Cycles Parameter Description CY14B101P Unit Min Max t RECALL RECALL Duration 200 µs t SS [11, 13] Soft Sequence Processing Time 100 µs Figure 28. Software STORE Cycle [13] Figure 29. Software RECALL Cy...

Page 28 - Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Write Latch not set

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 28 of 32 Hardware STORE Cycle Parameter Description CY14B101P Unit Min Max t DHSB HSB To Output Active Time when write latch not set 25 ns t PHSB Hardware STORE Pulse Width 15 ns Figure 30. Hardware STORE Cycle [9] ~ ~ ~ ~ HSB (IN) HSB (OUT) S...

Page 29 - Ordering Information; Ordering Code; Commercial; Part Numbering Nomenclature; P - Serial SPI nvSRAM with RTC

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 29 of 32 Ordering Information Ordering Code Package Diagram Package Type Operating Range CY14B101P-SFXCT 51-85022 16 SOIC Commercial CY14B101P-SFXC 51-85022 16 SOIC CY14B101P-SFXIT 51-85022 16 SOIC Industrial CY14B101P-SFXI 51-85022 16 SOIC Al...

Page 30 - Package Diagrams

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 30 of 32 Package Diagrams Figure 31. 16-Pin (300 mil) SOIC Package (51-85022) 51-85022 *B [+] Feedback

Page 31 - Document History Page; Submission

PRELIMINARY CY14B101P Document #: 001-44109 Rev. *B Page 31 of 32 Document History Page Document Title: CY14B101P 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock Document Number: 001-44109 REV. ECN NO. Submission Date Orig. of Change Description of Change ** 1939467 See ECN UNC/AESA New Dat...

Page 32 - Worldwide Sales and Design Support

Document #: 001-44109 Rev. *B Revised February 2, 2009 Page 32 of 32 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respectiveholders. PRELIMINARY CY14B101P © Cypress Semi...

Cypress CY14B101P - Manual

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