Cypress STK14CA8 - Manuals - manualsarea.com

Page 2 - Pinouts; Figure 3. Relative PCB Area Usage; Pin Descriptions; Pin Name

STK14CA8 Document Number: 001-51592 Rev. ** Page 2 of 16 Pinouts Figure 1. 48-Pin SSOP Figure 2. 32-Pin SOIC Figure 3. Relative PCB Area Usage [1] Pin Descriptions V SS A 14 A 12 A 7 A 6 DQ 0 DQ 1 V CC DQ 2 A 3 A 2 A 1 V CAP A 13 A 8 A 9 A 11 A 10 DQ 7 DQ 6 V SS A 0 NC 44 43 42 41 40 39 38 37 36 35 ...

Page 3 - Absolute Maximum Ratings; Absolute; DC Characteristics; STORE

STK14CA8 Document Number: 001-51592 Rev. ** Page 3 of 16 Absolute Maximum Ratings Voltage on Input Relative to Ground................. –0.5V to 4.1V Voltage on Input Relative to V SS ...........–0.5V to (V CC + 0.5V) Voltage on DQ 0-7 or HSB ......................–0.5V to (V CC + 0.5V) Temperature u...

Page 4 - AC Test Conditions; Figure 4; Capacitance

STK14CA8 Document Number: 001-51592 Rev. ** Page 4 of 16 AC Test Conditions Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times ................................................. ≤ 5 ns Input and Output Timing Reference Levels ......................

Page 7 - AutoStore/POWER UP RECALL

STK14CA8 Document Number: 001-51592 Rev. ** Page 7 of 16 AutoStore/POWER UP RECALL t Figure 10. AutoStore/POWER UP RECALL Note Read and Write cycles are ignored during STORE, RECALL, and while V CC is below V SWITCH. NO. Symbols Parameter STK14CA8 Units Notes Standard Alternate Min Max 22 t HRECALL ...

Page 8 - Software Controlled STORE/RECALL Cycle

STK14CA8 Document Number: 001-51592 Rev. ** Page 8 of 16 Software Controlled STORE/RECALL Cycle Figure 11. Software STORE/RECALL CYCLE: E Controlled [13] Figure 12. Software STORE/RECALL CYCLE: G Controlled [13] NO. Symbols Parameter [12,13] STK14CA8-35 STK14CA8-35 STK14CA8-45 Units Notes E Cont G C...

Page 9 - Hardware STORE to SRAM Disabled; Hardware STORE Pulse Width; Soft Sequence Processing Time

STK14CA8 Document Number: 001-51592 Rev. ** Page 9 of 16 Hardware STORE Cycle Figure 13. Hardware STORE Cycle Soft Sequence Commands Figure 14. Software Sequence Commands NO. Symbols Parameter STK14CA8 Units Notes Standard Alternate Min Max 31 t DELAY t HLQZ Hardware STORE to SRAM Disabled 1 70 μ s ...

Page 10 - Mode Selection; Mode

STK14CA8 Document Number: 001-51592 Rev. ** Page 10 of 16 Mode Selection E W G A 16 -A 0 Mode I/O Power Notes H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08B45 Read SRAMRead SRAMR...

Page 11 - nvSRAM Operation; nvSRAM; Figure 15. AutoStore Mode

STK14CA8 Document Number: 001-51592 Rev. ** Page 11 of 16 nvSRAM Operation nvSRAM The STK14CA8 nvSRAM has two functional components pairedin the same physical cell. These are the SRAM memory cell anda nonvolatile QuantumTrap cell. The SRAM memory celloperates similar to a standard fast static RAM. D...

Page 13 - Low Average Active Power; Figure 16. Current vs Cycle Time; Preventing AutoStore; AutoStore Disable

STK14CA8 Document Number: 001-51592 Rev. ** Page 13 of 16 Low Average Active Power CMOS technology provides the STK14CA8 with the benefit ofpower supply current that scales with cycle time. Less current isdrawn as the memory cycle time becomes longer than 50 ns. Figure 16 shows the relationship betw...

Page 16 - Document History Page; Worldwide Sales and Design Support

Document Number: 001-51592 Rev. ** Revised March 04, 2009 Page 16 of 16 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All other products and company names mentioned in this document may be the trademarks of theirrespective holders. STK14CA8 © Cypress Semic...