Cypress STK14CA8 - Manual
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Table of Contents:
- Page 2 – Pinouts; Figure 3. Relative PCB Area Usage; Pin Descriptions; Pin Name
- Page 3 – Absolute Maximum Ratings; Absolute; DC Characteristics; STORE
- Page 4 – AC Test Conditions; Figure 4; Capacitance
- Page 7 – AutoStore/POWER UP RECALL
- Page 8 – Software Controlled STORE/RECALL Cycle
- Page 9 – Hardware STORE to SRAM Disabled; Hardware STORE Pulse Width; Soft Sequence Processing Time
- Page 10 – Mode Selection; Mode
- Page 11 – nvSRAM Operation; nvSRAM; Figure 15. AutoStore Mode
- Page 13 – Low Average Active Power; Figure 16. Current vs Cycle Time; Preventing AutoStore; AutoStore Disable
- Page 16 – Document History Page; Worldwide Sales and Design Support
STK14CA8
128Kx8 AutoStore
™
nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-51592 Rev. **
Revised March 04, 2009
Features
■
25, 35, 45 ns Read Access and Read/Write Cycle Time
■
Unlimited Read/Write Endurance
■
Automatic Nonvolatile STORE on Power Loss
■
Nonvolatile STORE Under Hardware or Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited RECALL Cycles
■
200K STORE Cycles
■
20-Year Nonvolatile Data Retention
■
Single 3.0V + 20%, -10% Operation
■
Commercial and Industrial Temperatures
■
Small Footprint SOIC and SSOP Packages (RoHS Compliant)
Description
The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol-
atile QuantumTrap™ storage element included with each
memory cell. This SRAM provides fast access and cycle times,
ease of use, and unlimited read and write endurance of a normal
SRAM.
Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performing
and most reliable nonvolatile memory available.
R
O
W
DE
C
O
DE
R
IN
PUT BU
F
F
ER
S
COLUMN DEC
G
E
W
COLUMN I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
A
15
– A
0
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
Quantum Trap
1024 X 1024
STATIC RAM
ARRAY
1024 X 1024
STORE
RECALL
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
0
A
1
A
2
A
3
A
4
A
10
A
11
V
CC
V
CAP
Logic Block Diagram
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Summary
STK14CA8 Document Number: 001-51592 Rev. ** Page 2 of 16 Pinouts Figure 1. 48-Pin SSOP Figure 2. 32-Pin SOIC Figure 3. Relative PCB Area Usage [1] Pin Descriptions V SS A 14 A 12 A 7 A 6 DQ 0 DQ 1 V CC DQ 2 A 3 A 2 A 1 V CAP A 13 A 8 A 9 A 11 A 10 DQ 7 DQ 6 V SS A 0 NC 44 43 42 41 40 39 38 37 36 35 ...
STK14CA8 Document Number: 001-51592 Rev. ** Page 3 of 16 Absolute Maximum Ratings Voltage on Input Relative to Ground................. –0.5V to 4.1V Voltage on Input Relative to V SS ...........–0.5V to (V CC + 0.5V) Voltage on DQ 0-7 or HSB ......................–0.5V to (V CC + 0.5V) Temperature u...
STK14CA8 Document Number: 001-51592 Rev. ** Page 4 of 16 AC Test Conditions Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times ................................................. ≤ 5 ns Input and Output Timing Reference Levels ......................
